Description of the SPI configuration in TRM

Rainald Koch

I refer to page 1556 in SPNU515B, which is the TRM for a TMS570. I am unsure about "Input data is latched ..." in Table 28-2. Does it refer to the data from the master or from the slave? If it refers to the data from the master, I would expect a different wording, something like "The slave shall latch the data ...", and I would also not expect two traces with data in the four figures below. If it refers, however, to data from the slave, I wonder how the slave can drive D7 just before the first edge of the clock (Figures 28-9 and 28-11).

over 9 years ago

0 Bob Crosby over 9 years ago

TI__Guru 72500 points

It refers to both the data from the master to the slave and the data from the slave to the master. They are both latched on the same clock edge. In the modes with phase=1, the slave outputs the first data bit as soon as the data is written to the TX buffer, or if CS is used, as soon as CS goes low.

0 Rainald Koch over 9 years ago in reply to Bob Crosby

Intellectual 610 points

Thank you, Bob, for the quick answer.
Just another question regarding Figures 28-9 and 28-11: Is the final edge of the clock, after phase 8, correct?

0 Bob Crosby over 9 years ago in reply to Rainald Koch

TI__Guru 72500 points

Figures 28-9 and 28-11 are correct. Figures 28-8 and 28-10 are perhaps misleading as the "edge" at the very right side of the figure is really the first clock edge of the next transfer. (Assuming 8-bit transfers.)

0 Rainald Koch over 9 years ago in reply to Bob Crosby

Intellectual 610 points

Oops, I meant Figures 28-8 and 28-10.
Thank you. Thread may be closed.

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Description of the SPI configuration in TRM