Is there the way to increase code execution speed from SDRAM?

I have some issues on SDRAM-located code execution speed on TM4C129ENCPDT.

I've measured IRAM and SDRAM code execution speeds and compared it - execution from on-chip SRAM is 12 times faster than from SDRAM.

CPU frequency is 120 MHz, EPI for SDRAM works at 60 MHz clock.

I am using MT48LC4M16A2TG memory chip, which can work on speed up to 133 MHz, data bus width is 16 bits.

Here's part of my SDRAM initialization code:

//SDRAM initialization call:
SDRAMInit(ui32SysClock, EPI_SDRAM_CORE_FREQ_50_100 | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT);

uint16_t *SDRAMInit(uint32_t ui32SysClock, uint32_t ui32Config)
{
    //some GPIO initialization skipped

    //
    // Is our current system clock faster than we can drive the SDRAM clock?
    //
    if(ui32SysClock > 60000000)
    {
        //
        // Yes. Set the EPI clock to half the system clock.
        //
        EPIDividerSet(EPI0_BASE, 1);
    }
    else
    {
        //
        // With a system clock of 60MHz or lower, we can drive the SDRAM at
        // the same rate so set the divider to 0.
        //
        EPIDividerSet(EPI0_BASE, 0);
    }

    //
    // Sets the usage mode of the EPI module.  For this example we will use
    // the SDRAM mode to talk to the external 64MB SDRAM daughter card.
    //
    EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);

    //
    // Configure the SDRAM mode.  We configure the SDRAM according to our core
    // clock frequency, in this case we are in the 15 MHz < clk <= 30 MHz
    // range (i.e 16Mhz crystal).  We will use the normal (or full power)
    // operating state which means we will not use the low power self-refresh
    // state.  Set the SDRAM size to 64MB with a refresh counter of
    // 1024 clock ticks.
    //
    EPIConfigSDRAMSet(EPI0_BASE, ui32Config, 1024);

#ifdef USE_EPI_CODE_SPACE
    //
    // Set the address map to use the external code space.  The EPI0 is mapped
    // from 0x10000000 to 0x7FFFFFFF.
    //
    EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_CODE_SIZE_256MB |
                     EPI_ADDR_CODE_BASE_1));

    //
    // Set the EPI memory pointer to the base of EPI memory space.  Note that
    // g_pusEPISdram is declared as volatile so the compiler should not
    // optimize reads out of the memory.  With this pointer, the memory space
    // is accessed like a simple array.
    //
    pusSDRAM = (unsigned short *)CODE_MAPPING_ADDRESS;
#else
    //
    // Set the address map.  The EPI0 is mapped from 0x60000000 to 0xCFFFFFFF.
    //
    EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6);

    //
    // Set the EPI memory pointer to the base of EPI memory space.  Note that
    // g_pusEPISdram is declared as volatile so the compiler should not
    // optimize reads out of the memory.  With this pointer, the memory space
    // is accessed like a simple array.
    //
    pusSDRAM = (unsigned short *)SDRAM_MAPPING_ADDRESS;
#endif

	//some unnecessary code skipped

}

So, is there some tricks with EPI to increase SDRAM speed?