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LM3S1621 HFAULTSTAT register FORCED bit

Shinji Ueda
Expert 5440 points
Hi, champs
My customer has quesitons about Stellaris.
Could you support this?
 
1. In datasheet P.156
Hard Fault Status (HFAULTSTAT)
Bit 30 FORCED
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
 
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
 
It can be read that there is several reason from which this bit set to 1.
Could you teach me all factors from which this bit set to 1?
 
2. Do you know the way to reset "How to keep setting of GPIOs High or Low condition"?
Custome is thinking VECTRESET bit to use now.
Is it OK?

If you have other way, please let me know.
Since there is no customer specific information in this post, I would suggest moving it to the TI forum.
  • 0
    Prodigy 80 points
    We got a couple of additional question from our customer.
    Could you give us any advice, please?
    Additional Question 1
    After executing VECTRESET, LM3S1621 can't transit "0x0000.0000(FLASH)".
    And it transited ROM area. So, Do you know what kind of code working on ROM area ?
    Our customer would like to know its mechanism.
    Additional Question 2
    Do you know the factor of "Hard Fault" ?
    In this time, "Hard Fault" means the access to reserved area which is 0x4002.451C.
    If you have an avoidance method for this Hard Fault, please tell us the workaround.
    The detail of customer situation
    They got a Hard Fault(FORCE) in spite of executing VECTRESET.
    It seems the below step by using Step-EXE after VECTRESET.
    1.Transit ROM area 0x0100.0C4C
    2.0x0100.0BB8~0x0100.0BFA
    3.occur the Hard Fault
    I am guessing that the bus fault has promoted occurred to the hard faults (FORCE).
    Because, PRECISE of FAULTSTAT register has become a 1 and FAULTADDR was
    the 0x4002.451C (Reserved area).
    Thanks!
  • 0
    TI__Mastermind 22640 points
    Hello Shinji,

    The hard fault is a Cortex M4 implementation and not specific to TM4C. Please refer the following Application note for more information on Faults and how to debug them: www.ti.com/.../spma043

    Thanks,
    Sai
  • 0 in reply to Sai Reddy
    Guru 47900 points

    Note that poster's MCU is the (long) discarded Cortex M3 (only discarded here, not M4) and M3 (also) generated & supports hard faults.

    As poster's M3 MCU is no longer produced - unless poster has substantial volume (which proves doubtful due to the nature of this post) - movement to the higher performing (and available) M4 MCUs appears to make great sense.