how to diagnose cache

Hi Eric,

 Please refer to the RM57L datasheet for the complete table. Below I'm showing a snippet of the cache memories in terms of PBIST RAM grouping. The Cache memories are mapped to group 31 and 32 for the Icache and Dcache. You can initiate PBIST March-13 test on these memories just like other memories in your startup.

Hi, Charles

Thank you for your detail information.

I am new to the PBIST, I want to know if the PBIST can be run just in the startup or can also run in the normal application. If run in the application if the normal application data (in RAM or cache) need to be saved and restored.

Hi Eric,
Yes, in theory you can run PBIST in runtime. However, it may not be the most practical thing to do. PBIST test is a destructive test where the selected RAM or cache will be subject to the test vectors. Your application data will be lost due to the test unless you first save the context and later restore them after the test. In the case of cache, you will need to invalidate the cache after the test. You will have some performance lost as the CPU needs to refill the cache again as each CPU read will be a cache miss. Your application needs to decide if runtime PBIST or LBIST is mandatory to meet your safety goal. If your application is in such an environment that the MCU is never powered off then perhaps running the PBIST in application is required. If not, then I think running PBIST in startup should be sufficient. At the end, you will need to decide for your application.

Hi Charles,

Is it possbile run a March-C algorithm by the application to diagnose the cache?

Hi Eric,

  What is March-C algorithm? Do you mean March13n algorithm? Please see below table in the TRM. As I mentioned in the prior reply the Instruction cache and Data cache are mapped to RAM group 31 and RAM 32. If you look at the table these RAM are the single port RAM that can be tested using march13n algorithm. 

Hi Charles,

Yes, the March-C is similar to march-13n.
I don't know what is meaning of single_port or two_port here?

Best regards,
Eric

Hi Charles,

I don't know why I can't see the Verify Answer button in this post. Could you close it?

regards,

Eric

Hi Eric,
I don't see the Verify Answer button either. I will close the thread if you don't have further questions. Thanks.

Hi Charles,

Would you please explain the difference between the single_port and two_port? (Memories under test)

HI Eric,
These are two different types of memory implementation. Single port RAMs are clocked RAM and as the name suggests, it has only one port. You can read or write to the single port RAM via its one-port interface. The two port RAM are normally asynchronous memory. They have two ports which allows read and write to the memory at the same time. From an user point of view you don't really need to care this detail.

Hi Charles,

thanks, you can close this thread now.

HI Eric,
I will close the thread.