Dear all,
I would like to confirm a way how to workaround the DEVICE#39 Erratum if using TMS570LC4357 in the 1st Silicion revision A.
Is the ONLY one working and forth-compatible with the Silicon Rev B as depicted in the forum thread e2e.ti.com/.../1408027 ?
Is that the must to logically multipy the signals of nDMQ0 and nDMQ1?
Is it sufficient to have only OR-gate with inputs of nWE signal and nDMQx? If the EMIF is running in 8-bit data mode, the signal nDMQx must be equal to the "lower" nDMQ0?
By the way, the document "SPNZ180D–June 2013–Revised May 2016" declares:
"There is no way to suppress the extra OE signals by hardware. However, user can left shift the address (2 bit for 16 bit EMIF and 3 bit for 8 bit EMIF) and use external hardware to only allow the first OE pulse to pass. Extra read cycles will be wasted. "
May you explain what is meant by "external hardware to only allow...."?
Do you mean not to connect EMIF lowest address signals A0, BA1 and BA0 to the external device (e.g. FPGA or memory)? The 1st address pin A0 of the external device will be connected to A1 of EMIF? Thanks to 3-bit-left-shift, the Byte access to data within the external device will be then performed just by incrementing / toggling of the A1 address pin, right?
Thanks for your clarification,
Jiri
