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lockstep

eric
Intellectual 885 points


Hi,

I want to confirm if my understanding about lockstep is correct.

see the following screenshot.

There are two sets of registers in each core? what about the ALU, Decode, components, also each core has a seperate one?

what about the cache and RAM? do they share the same one cache?

I also don't understand the "the CPU pushed the internal registers on to the stack on a function call, which could lead to the detection of the core comparision error", why this happens?

  • 0
    TI__Guru 72500 points
    Eric, would you please tell me which Hercules device you are asking about. The devices that use the Cortex R4F are not cache based. The Flash is attached to the ATCM and static RAMS are attached to the BTCMs. The blocks labeled CPU1 and CPU2 in the first diagram are complete Cortex R4F CPUs.
  • 0 in reply to Bob Crosby
    Intellectual 885 points
    Hi Bob,

    RM57L(cortexR5F) and RM48L(cortexR4F).

    For RM48L the two core have seperate registers? Can I think that the CCM will compare the ATCM, BTCM, AXI bus signals? (according the processor block diagram these signals are output of the core)

    For RM57L a I-Cache and D-Cache exist. Do the two cores share the cache or each core has a cache?

    Best regard,
    Eric
  • 0 in reply to eric
    TI__Guru 72500 points
    Yes, on the RM48L, the CCMR4 is constantly checking the ATCM, BTCM and AXI signals between the two CPUs. Each CPU has its own registers.

    On the RM57L both CPUs see the same I-cache and D-cache. The CCMR5 is checking the signals between the CPUs and the caches.