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Flash & RAM is locked

jia lian
Intellectual 280 points
Other Parts Discussed in Thread: RM57L843, UNIFLASH

My chip is RM57L843.

My MPU configuration is as below:

{
region 1:
0x00000000
0xFFFFFFFF
NORMAL_OINC_NONSHARED
PRIV_NA_USER_NA_NOEXEC

region 2:
0x00000000
0x003FFFFF
NORMAL_OINC_NONSHARED
PRIV_RO_USER_RO_EXEC

region 3:
0x08000000
0x0807FFFF
NORMAL_OINC_NONSHARED
PRIV_RW_USER_RW_EXEC

region 4:
0x08400000
0x0847FFFF
NORMAL_OINC_NONSHARED
PRIV_RW_USER_RW_NOEXEC

region 5:
0x30000000
0x30FFFFFF
STRONGLYORDERED_SHAREABLE
PRIV-RW_USER_RW_NOEXEC

region 6:
0x34000000
0x37FFFFFF
NORMAL_OINC_NONSHARED
PRIV_NA_USER_NA_NOEXEC

region 7:
0x60000000
0x63FFFFFF
STRONGLYORDERED_SHAREABLE
PRIV_RW_USER_RW_EXEC

region 8:
0x64000000
0x67FFFFFF
STRONGLYORDERED_SHAREABLE
PRIV_RW_USER_RW_EXEC

region 9:
0x68000000
0x6BFFFFFF
STRONGLYORDERED_SHAREABLE
PRIV_RW_USER_RW_EXEC

region 10:
0x80000000
0x87FFFFFF
NORMAL_OINC_NONSHARED
PRIVE_RW_USER_RW_EXEC

region 11:
0xF0000000
0xF07FFFFF
NORMAL_OINC_NONSHARED
PRIV_RW_USER_RW_NOEXEC

region 12:
0xFB000000
0xFBFFFFFF
DEVICE_NONSHAEABLE
PRIV_RW_USER_RW_NOEXEC

region 13:
0xFC000000
0xFCFFFFFF
DEVICE_NONSHAREABLE
PRIV_RW_USER_RW_NOEXEC

region 14:
0xFE000000
0xFEFFFFFF
DEVICE_NONSHAREABLE
PRIV_RW_USER_RW_NOEXEC

region 15:
0xFF000000
0xFFFFFFFF
DEVICE_NONSHAREABLE
PRIV_RW_USER_RW_NOEXEC

region 16:
0xFFF80000
0xFFFFFFFF
DEVICE_NONSHAREABLE
PRIV_RW_USER_RW_NOEXEC
}

Now, I transplant SafeRTOS to RM57L843.

My RM57_flash.icf is as below.

{
define symbol __ICFEDIT_intvec_start__ = 0x00000000;

define symbol __ICFEDIT_region_ROM_start__ = 0x00000020;
define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x08001500;
define symbol __ICFEDIT_region_RAM_end__ = 0x0807FFFF;

define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_svcstack__ = 0x100;
define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x100;
define symbol __ICFEDIT_size_undstack__ = 0x100;
define symbol __ICFEDIT_size_abtstack__ = 0x100;
define symbol __ICFEDIT_size_heap__ = 0;

define memory mem with size = 4G;

define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];

define symbol __total_stack_size__ =
__ICFEDIT_size_cstack__ +
__ICFEDIT_size_svcstack__ +
__ICFEDIT_size_fiqstack__ +
__ICFEDIT_size_irqstack__ +
__ICFEDIT_size_abtstack__ +
__ICFEDIT_size_undstack__;

define region STACK = mem:[from 0x08000000 size __total_stack_size__];

define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];

define symbol __region_DRAM_start__ = 0x80000000;
define symbol __region_DRAM_end__ = 0x807FFFFF;
define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__];

define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

initialize by copy { readwrite };

do not initialize { section .noinit };

define block __kernel_functions_block__ with alignment = 8, size = 0x8000 - 0x60
{ section __kernel_functions__ };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvecs, block __kernel_functions_block__ };

place in ROM_region { readonly };

define block __kernel_data_block__ with alignment = 0x800, size = 0x800
{
section __kernel_data__,
section __kernel_nz_data__,
};

define block __safety_diagnosis_data_block__ with alignment = 0x400, size = 0x400
{ section __safety_diagnosis_data__ };

define block __safety_iec_data_block__ with alignment = 0x1000, size = 0x1000
{ section __safety_iec_data__ };

define block __specified_data_block__ with alignment = 0x20000, size = 0x20000
{ section __specified_data__ };

define block __idle_task_data_block__ with alignment = 0x20, size = 0x20
{
section __idle_task_data__,
section __idle_task_zero_data__
};

place in RAM_region
{
readwrite,
block __kernel_data_block__,
block __safety_diagnosis_data_block__,
block __safety_iec_data_block__,
block __specified_data_block__,
block __idle_task_data_block__,
block HEAP
};

place in DRAM_region { section DRAM };

export symbol __ICFEDIT_intvec_start__;
export symbol __ICFEDIT_region_ROM_start__;
export symbol __ICFEDIT_region_ROM_end__;
}

My task is set PRIVILEGED.

After I tried to burn the program into RM57L843, CPU seems to be locked. Because I can't burn any program into RM57L843 any more afterwards.

When I burned the program, the error message box will be popped up. refer to below.

"Error connecting to the target:
(Error -2062 @ 0x0)
Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK).
(Emulation package 6.0.14.5)"

I tried to erase flash using UniFlash. When I clicked erase before releasing RST button in a little time on evaluation board, the flash seems to be connected, but failed in access RAM address. Error message is as below.

[11:34:54] Erasing flash sectors on Core 0 < Texas Instruments XDS100v2 USB Debug Probe/CortexR5 > ...
[11:34:54] Begin Erase Flash operation.
[11:34:54] CortexR5: GEL Output:  Memory Map Setup for Flash @ Address 0x0
[11:34:55] CortexR5: Erasing Flash memory...

[11:34:57] Target failed to read 0x08000000
[11:34:58] Operation Erase Flash returned.

 

How can I do something to solve this issue? How can I unlock the RAM access?

Is there something error for my MPU configuration?

 

 

  • 0
    TI__Guru 72500 points
    Can you connect with CCS and do a system reset?
  • 0 in reply to Bob Crosby
    Intellectual 280 points
    Hi, Bob:
    1> When I tried to burn the program into RM57L843 by CCS 6.1.1, a error prompt will be popped up.
    Error connecting to the target:(Error -1170 @ 0x0)
    Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK).
    (Emulation package 6.0.14.5)
    2> When I tried to connect RM57L843 by Target Configurations. The test Connection is as below.
    [Start: Texas Instruments XDS100v2 USB Debug Probe_0]Execute the command:
    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
    [Result]
    -----[Print the board config pathname(s)]------------------------------------
    C:\Users\alian\AppData\Local\TEXASI~1\CCS\ ti\0\0\BrdDat\testBoard.dat
    -----[Print the reset-command software log-file]-----------------------------
    This utility has selected a 100- or 510-class product.
    This utility will load the adapter 'jioserdesusb.dll'.
    The library build date was 'Sep 4 2015'.The library build time was '21:59:23'.
    The library package version is '6.0.14.5'.
    The library component version is '35.35.0.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '4' (0x00000004).
    The controller has an insertion length of '0' (0x00000000).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.
    -----[Print the reset-command hardware log-file]-----------------------------
    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the FTDI FT2232 with USB interface.
    The link from controller to target is direct (without cable).
    The software is configured for FTDI FT2232 features.
    The controller cannot monitor the value on the EMU[0] pin.
    The controller cannot monitor the value on the EMU[1] pin.
    The controller cannot control the timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '0' (0x0000).
    -----[The log-file for the JTAG TCLK output generated from the PLL]----------
    There is no hardware for programming the JTAG TCLK frequency.
    -----[Measure the source and frequency of the final JTAG TCLKR input]--------
    There is no hardware for measuring the JTAG TCLK frequency.
    -----[Perform the standard path-length test on the JTAG IR and DR]-----------
    This path-length test uses blocks of 64 32-bit words.
    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.
    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.
    -----[Perform the Integrity scan-test on the JTAG IR]------------------------
    This test will use blocks of 64 32-bit words.
    This test will be applied just once.Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0All of the values were scanned correctly.
    The JTAG IR Integrity scan-test has succeeded.
    -----[Perform the Integrity scan-test on the JTAG DR]------------------------
    This test will use blocks of 64 32-bit words.
    This test will be applied just once.Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0All of the values were scanned correctly.
    The JTAG DR Integrity scan-test has succeeded.
    [End: Texas Instruments XDS100v2 USB Debug Probe_0]
    3> After I clicked system reset in Target Configurations, the scene is the same.