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Software read back of SRAM configuration

Mike Ashman
Intellectual 430 points
Other Parts Discussed in Thread: HALCOGEN

In trying to satisfy safety feature RAM11 (Software read back of written configuration) in the Hercules safety manual I am using the Halcogen API call sramGetConfigValue to read the, among others, tcramNReg->RAMINTCTRL register. To verify that the contents of this register haven't changed I call sramGetConfigValue to read the initial setting and then again to read the current setting and I compare the values. In the case of the RAMINTCTRL register my initial setting is 1 (which according to the tech. reference manual means that single bit error correction interrupt is enabled) but when I read the current value it is 0. Why the difference? I am not manually setting the value of this register to 0 anywhere in the code. Isn't the initial setting (the Halcogen variable SRAM_RAMINTCTRL_CONFIGVALUE) set by Halcogen? Why would the actual current setting be 0 if I haven't manually written to this register?

  • 0
    TI__Guru 72500 points

    You did not mention which Hercules part you are using, but yes HALCoGen does set the single error interrupt enable bit in IntCtrl. Do you see it set in the CCS register window?

  • 0 in reply to Bob Crosby
    Intellectual 430 points
    Hi Bob,
    We are using TMS570LS04X. When I look at that register value I see that it's 0, which is the same value I get with sramGetConfigValue for the current Value. Why does Halcogen have the SRAM_RAMINTCTRL_CONFIGVALUE, which is what is used to return the initial value from sramGetConfigValue to 1? And where in the Halcogen tool can I change this value?
    Thanks
    MIke
  • 0 in reply to Mike Ashman
    TI__Guru 72500 points

    The SRAM_RAMINTCTRL_CONFIGVALUE is 0 after reset. In HALCoGen the startup code calls the function checkRAMECC() (in the file sys_selftest.c). That function writes 1 to the RAMINTCTRL bits (there are two bits, one for odd the other for even locations).  If in HALCoGen you disable (uncheck the box) the "ESRAM ECC Check" on the "SAFETY INIT" tab, the checkRAMECC() function is not called and the RAMINTCTRL bits  will not be set.

  • 0 in reply to Bob Crosby
    Intellectual 430 points

    Thanks Bob, but when I read SRAM_RAMINTCTRL_CONFIGVALUE it is set to 1, not 0 as you say. I currently do not have the ESRAM ECC Check selected so my RAMINTCTRL register bits are 0. I would expect the SRAM_RAMINTCTRL_CONFIGVALUE to be set to 0 as well but since it is 1 my register check fails. Obviously I could just skip checking this register as part of my RAM11 safety check but I would like to understand what is going on and verify that this is not a problem.

  • 0 in reply to Mike Ashman
    Intellectual 430 points

    Here is  screenshot of my Halcogen settings

  • 0 in reply to Mike Ashman
    TI__Guru 72500 points
    The initial value for bit 0 of the RAMINTCTRL register is 0. If you do not enable the ESRAM ECC check, or do not explicitly write that bit, it will remain 0. I admit that the comment in line 484 of system.h "/* Configuration registers initial value */" is misleading in that it assumes all of the default tests were run. Is there some reason why you chose to disable the ESRAM ECC check?