Decoupling capacitor present on each power pin ?

Hello Chris,

Normally a 0.1uF should be there on every VDD pin. A 1.0uF can be placed in place of a 0.1uF for one VDD pin. Refer to schematic in the following reference design.

www.ti.com/.../TIDM-TM4C129POE

Hello Amit, 

I didn't understand well. Is it one or two capacitor which should be incluided on each VDD pin ?

Hello Chris

Did you check the reference design link I sent?

yes but it is unclear. how do we know which capaictor is allocated to which pin on the reference design ?

Hello Chris

I have allocated 0.1uF to each of the VDD/VDDA pin. Where there are a few 0.1uF together, I have used a 1.0uF

Amin,
Can you please confirm CLEARLY how many and which value of decoupling capacitor should be placed on each pin.
Thanks

Hello Chris

Then I would suggest checking the layout file for the reference design or referring to the System Design Guidelines application note for TM4C129x device.

Amit,
What I am asking is not complicated i suppose but your answers are not clear enough :
A = How many capacitor needed on each pin, 1 or 2 ?
B = value of each capacitor for 1 or 2
Regards

Hello Chris

Each pin needs only 1 capacitor. You need both bulk capacitor of 1.0uF and noise decaps 0.1uF. So these need to be distributed 1 per pin.

Amit,
Ok, so how do we know which pin get the bulk and which pin get the noise decaps ?

Hello Chris

We do not have a recommendation on which pin gets what. Normally, my thumb rule is to have a 1.0uF cap where there are already multiple 0.1uF placed close by.

ok, last question:
do we fill equally bulk capacitor and noise cancelling capacitor 1 for 1 on all the VDD pin of the chip or do we have to respect some other rules ? Is there are total capacitor value to reach with all those capacitor ? Can you please illustrate your answer with an example for example for TM4C123GH6PGE, there are 12 pin for VDD. Would you use 6 capacitor for bulk and 5 capacitor for noise cancelling equally spreaded on the 4 side of the chip ?

Hello Chris

As per the recommendation in the System Design Guidelines

"The combined VDD and VDDA bulk capacitance of the microcontroller is typically between 2 μF and 22 μF, with values on the upper end of that range providing measurable ripple reduction in some applications, especially if the circuit board does not have solid power and ground planes"

If there are total 12 pins for VDD and VDDA, I would go for 1 x 1.0uF + 11 x 0.1uF to get a total of 2.1uF caps. From a distribution I would spread them out keeping the 1.0uF on the side where the most VDD+VDDA pins are placed.

Thank you Amit. Your remarks is helpfull.

Hello Chris

For the forum: My distribution of the pins is based on my experience and I have not tried any other combination....

A slightly different perspective from the peanut gallery.

I generally use the following rules of thumb
For high speed (10 Mhz or more) processors the first capacitor is the ground and power plane. Low capacitance, low inductance it is very high speed.
Then each power pin gets a 0u01 and a 0u1 capacitor near the pin. These cover different frequency ranges.
The chip as a whole gets local bulk capacitance to buck out any power distribution inductance. Normally 4-10u.

Yes, this is probably overkill, but that's the objective. Small capacitors take little space and are cheap. Scrimping doesn't buy you much and dealing with inadequate decoupling is difficult to troubleshoot and fix after the fact.

One other thing to watch is the capacitor quality. The 0u01 and 0u1 should be X7R or better. The bulk capacitors can be more tolerant.

There are variations on the approach and multiple ways of achieving the same affect

Robert

Robert, 

Your post is probably usefull but I didn't understand and visualize it well. 

It would be good to have a simple scheme even made on a piece of paper and taken with a camera to better visualize your prposal to place capacitor on which pin exactly.

I'm not sure how I can be more explicit than 'each power pin'.

Robert

this : " the first capacitor is the ground and power plane" and "0u01 and a 0u1"

Hello Chris

Like I had mentioned earlier, going through the CAD files may be more useful. Robert mentioned the rule of thumb he follows, you have to check which method is most optimal for your design.

Chrischina said:

this : " the first capacitor is the ground and power plane"

The ground and power planes form a capacitor (Two metal planes separated by a dielectric). It is a small capacitor since the planes are far apart but it does play a role. Basically I'm suggesting you don't try to save money by using a two layer board or otherwise removing the power planes.

Chrischina said:

"0u01 and a 0u1"

That's a standard notation for capacitance values. The SI prefix replaces the decimal notator (u replaces the Greek micron since it is similar in appearance and present on a standard keyboard). It saves confusion due to

• whether , or . is the decimal separator. IE you cannot know if 2,000 is two or two thousand without more context
• faded decimal notators or extra ones (ink spots, pen points, fly spots etc...)

Robert