calling IntDisable from a task is causing a hard fault

void EPI_Init(void) {
	uint16_t status;
	 int16_t count;

	//-------------------------------------------------------------
	// Disable all
	//-------------------------------------------------------------
	// Set pointer to EPI memory mapped window.
	g_pusEPIFPGA = (uint16_t *)0xC0000000;

	//clear the FIFO interrupt triggers
	IntPendClear(		INT_EPI0);
	IntDisable( 		INT_EPI0);
	EPIIntErrorClear(	EPI0_BASE, 0xFF);
	EPIIntDisable(		EPI0_BASE, 0xFF);

	// Put the attributes in a known state for the uDMA EPI channel.
	uDMAIntClear(		UDMA_CH20_EPI0RX);
	uDMAIntClear(		UDMA_CH21_EPI0TX);
	uDMADisable();

	uDMAChannelDisable(	UDMA_CH20_EPI0RX);
	uDMAChannelDisable(	UDMA_CH21_EPI0TX);

	uDMAChannelAttributeDisable(UDMA_CH20_EPI0RX, UDMA_ATTR_ALL);
	uDMAChannelAttributeDisable(UDMA_CH21_EPI0TX, UDMA_ATTR_ALL);

	uDMAChannelControlSet(UDMA_CH20_EPI0RX, UDMA_DST_INC_NONE | UDMA_SRC_INC_NONE);
	uDMAChannelControlSet(UDMA_CH21_EPI0TX, UDMA_DST_INC_NONE | UDMA_SRC_INC_NONE);


	//-------------------------------------------------------------
	// Configure the EPI interface
	//  - speed
	//  - operation mode
	//  - configuration registers
	//-------------------------------------------------------------
	//disable EPI
	EPIModeSet(		EPI0_BASE,
					EPI_MODE_DISABLE);
	EPIDividerSet(	EPI0_BASE,
					EPI_DIV_FACTOR_DATA);
	EPIModeSet(		EPI0_BASE,
					EPI_MODE_HB16);
    EPIConfigHB16Set(EPI0_BASE,
//					EPI_HB16_USE_TXEMPTY          |		//Tx fifo empty enable
//					EPI_HB16_USE_RXFULL           |		//Rx fifo full enable
//					EPI_HB16_BURST_TRAFFIC        | 	//burst mode enabled
					EPI_HB16_IN_READY_EN          |  	//IRDY enabled
					EPI_HB16_IN_READY_EN_INVERTED |		//IRDY polarity inverted
					EPI_HB16_MODE_ADDEMUX         | 	//sets up data and address as separate
					EPI_HB16_CSCFG_ALE            |		//EPIS030 to operate as an address latch (ALE)
					EPI_HB16_ALE_HIGH             |		//sets the address latch active high
					EPI_HB16_WRWAIT_0             |		//sets write wait state to 2 EPI clocks.
					EPI_HB16_RDWAIT_0             , 	//sets read wait state to 2 EPI clocks.
					0xF0);								//FIFO mode	maximum number of clocks
	EPIConfigHB16TimingSet(EPI0_BASE,
					0			,						//specifies the chip select to configure[0-3]
					EPI_HB16_IN_READY_DELAY_1     |   	//sets the stall on input ready (EPIS032)
														//to start 1 EPI clock after signaled
					EPI_HB16_WRWAIT_MINUS_ENABLE  |		//enables a 1 EPI clock write wait state reduction
					EPI_HB16_RDWAIT_MINUS_ENABLE); 		//enables a 1 EPI clock read wait state reduction

	//setup the address mapping for low level driver
	EPIAddressMapSet(EPI0_BASE,
					EPI_ADDR_PER_BASE_C   |
					EPI_ADDR_PER_SIZE_64KB);
	EPIFIFOConfig(	EPI0_BASE,
					EPI_FIFO_CONFIG_TX_1_2 |			//2/4 words
					EPI_FIFO_CONFIG_RX_1_2);			//4/8 words

	//configure the EPI Non blocking read
	EPINonBlockingReadConfigure(EPI0_BASE,
					0,
					EPI_NBCONFIG_SIZE_16,
					0);

	//-------------------------------------------------------------
	// Setup the EPI interrupt to service the NBRFIFO and the WFIFO
	// When the NBRFIFO is full, or the WFIFO is empty generate an
	// interrupt or trigger a uDMA transfer to service the buffer
	//-------------------------------------------------------------
	//setup the interrupt mask for the EPI.
	//Note: interrupt masking has no effect on uDMA, which
	//      operates off the raw source of the read/write
	//      interrupts
	//Note: we dont want to enable the EPI Rx and Tx interrupt,
	//      the EPI fifos will be serviced by the uDMA
	EPIIntEnable(	EPI0_BASE,
//					EPI_INT_RXREQ       |				//read FIFO above trigger level
//					EPI_INT_TXREQ       |				//transmit FIFO below trigger level
					EPI_INT_DMA_TX_DONE |				//transmit DMA completes
					EPI_INT_DMA_RX_DONE |				//read DMA completes
					EPI_INT_ERR);						//error condition

	// Enable the EPI interrupt on the processor (NVIC).
	// Note: even if no EPI interrupt were enabled, the uDMA
	//       controller will generate an interrupt on the EPI
	//       interrupt signal when a uDMA transfer is complete.
	IntEnable(INT_EPI0);

	//-------------------------------------------------------------
	// Configure the uDMA for the EPI read and write
	// Make sure the uDMA is configure before calling those functions
	// i.e. call A_uDMA.c/uDMA_init( ).
	//-------------------------------------------------------------
	// Put the attributes in a known state for the uDMA EPI channel.
	uDMAChannelAssign(UDMA_CH20_EPI0RX);
	uDMAChannelAssign(UDMA_CH21_EPI0TX);

	// Set the USEBURST attribute for the uDMA EPI RX/TX channel.
	// and allow the peripheral to generate software request for uDMA channel
	uDMAChannelAttributeEnable(	UDMA_CH20_EPI0RX,			//NBRFIFO
								UDMA_ATTR_USEBURST       |	//single request is not supported
								UDMA_ATTR_HIGH_PRIORITY);	//needed for ADC transfers
	uDMAChannelAttributeEnable(	UDMA_CH21_EPI0TX,			//WFIFO
								UDMA_ATTR_USEBURST);		//single request is not supported

	// Configure the control parameters for the EPI RX/TX.  The uDMA EPI RX/TX
	uDMAChannelControlSet(		UDMA_CH20_EPI0RX,			//NBRFIFO
								UDMA_SIZE_16       |		//data size
								UDMA_SRC_INC_NONE  |		//no source address increment
								UDMA_DST_INC_16    |		//destination address increment
								UDMA_ARB_4);				//arbitration size
	uDMAChannelControlSet(		UDMA_CH21_EPI0TX,			//WFIFO
								UDMA_SIZE_16       |		//data size
								UDMA_SRC_INC_16    |		//source address increment
								UDMA_DST_INC_16    |		//destination address increment
								UDMA_ARB_2);				//arbitration size
	uDMAEnable();
}