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Influence of error detection of EFuse controller

Haggy
Intellectual 440 points

When it detects an error of EFuse controller, I want to know the impact on the microcomputer.
Does it affect to CPU function?
Does it affect to the flash and SRAM read and write function?
If it affects the CPU or memory, please tell me the contents of the impact.
Please tell me if there are other effects.

  • 0
    TI__Guru**** 190456 points

    Hi Haggy,

      It depends when the error is detected and the severity of the error. After power up reset, the eFuse controller automatically reads the values of the eFuses and shifts them into registers. This operation is known as the efuse autoload sequence. These values stores in the registers are used to control some of the on-chip modules such as flash banks, pump and SRAM array. If there is failure during the efuse autoload sequence then the values read from the eFuses can not be relied on. All device operations should be considered unreliable. An error pin is asserted in this situation. So to answer your question, yes, it will affect the CPU function as the code the CPU is reading from which is stored in the flash may not be reliable due to incorrect Efuse values to control the flash banks and pump. 

  • 0 in reply to Charles Tsai
    TI__Guru**** 190456 points
    I want to make one correction. The AJSM password is stored in the Customer OTP starting at 0xF0000000 while the system parameters are stored in the TI OTP.
  • 0 in reply to Charles Tsai
    TI__Guru**** 190456 points
    Hi Haggy,

    Is your question answered? if your question is answered can you please click the 'Verify Answer' button to close the thread. Thanks.