The issue about invalidating data cache

How can I invalidate the partially cache?
Above my scheme about Ethernet receiving and transmiting is available? Is there any comment solution about consistency between cache and EMAC for RM57L843 ?

I have 003 example for lwip and RM57L843, but I don't very make clearly how solve data consistency between EMAC and cache for RM57L843. I saw the example enables cache and it don't use invalidate cache solution in any place, and although I set entire RAM to write-through, it keep ethernet communication is ok. Who can explain 003 example to me? It seems different with my solution.

Hello,

Invalidating the entire d-cache might cause data lose as data which wasn't already written back to the SRAM will be invalidated, that might be the reason for the abort you are facing.

The device features a so called Micro Snooping Control Unit (uSCU) on the other hand, this unit ensures data coherency between the d-cache and other masters (e.g. DMA and Ethernet) on Write-Trough regions.

The uSCU is briefly explained in the TRM:

The uSCU which is part of the Cortex-R5 processor system contains an ACP
(Accelerator Coherency Port) interface which provides snoop capabilities on
write-transactions coming from the non-CPU masters. Transactions are
received on the ACP-S slave port, and transmitted on the memory system via
the ACP-M master port. The ACP automatically invalidates the appropriate
Level 1 data-cache lines at the appropriate time, allowing software maintenance
free cache coherency for data in write-through cache regions, as well as noncached.

With this you should get around any cache maintenance, however DMB instructions might be needed to ensure that writes to the SRAM from CPU happened before proceeding configuring the EMAC.

Best Regards,
Christian

Hello, Herget:
Is uSCU feature of RM57L843 always available? Does it need to be enabled by manual? If it needs to enable, how can I enable uSCU feature?
Now, I explain my met issue.
Previously, my project can be worked very well. My project is RM48L952 + lwip + safeRTOS.
Now, I want to change CPU from RM48 to RM57L843.
I found my project's ethernet feature can't work very well. It can't transmit and receive data. Afterwards, I set the lwip MPU region to write-through, so RM57 can successfully transmit ethernet data, but don't always receive correct etherent data. Once I turn off the cache, it can successfully receive etherent data.
But, I can't turn off the cache due to other feature. I want to just invalidate the cache when receiving etherent data.
Do you have any solution to solve my problem? I think my issue is so common for consistency between EMAC and cache, TI should have solution to keep consistency for etherent transmitting.

Hello Christian,

Would you please help me to check my source code?

I want to communicate with host using RM57L843.

Now, I can transmit ethernet data to host, which captured by wireshark. But it doesn't always receive etherent packet, and discade packet ratio is 70%.

I debug it and found some received packet is entire zero. Once I disable entire cache, it can works very well. Why?

7242.SOC_v1.zip

Hi, did you configured the memory region with the ethernet packages as Write Through in the MPU?

Could you please add a DMB instruction in your code right before you are going to read a package and see if this helps?

Thanks,
Christian