About Level 2 and Level 3 (L2 and L3) Interconnect Subsystem

I am reading "Safety Manual for TMS570LS31x and TMS570LS21 x Hercules?ARMR-Based Safety Critical Microcontrollers (Literature Number: SPNU511D)".

I can not understand the contents of the "Level 2 and Level 3 (L2 and L3) Interconnect Subsystem".

Do you have such as a block diagram showing the "Level 2 and Level 3 (L2 and L3) Interconnect Subsystem" ?

Or, Do you have any understandable information in manuals and data sheets?