How do erase flash after executing program line NOXTAL and MOSC is silent.

Hi Chuck,

Clearing the NOXTAL bit should not have had effect of killing PIOSC which is set default oscillator in RSCLKCFG for flash and EEROM until MOSC is set as the clock source. Either way there must be some way to erase flash in PIOSC clock mode just after POR.

I just cleared the bit as it said to do assuming PIOSC was default clock source prior to configuring MOSC as the run source in RSCLKCFG REG 11, 0x0b

MOSCCTL REG10 0x7c

NOXTAL[2]: 0  RST=1 This bit should be cleared when a crystal or oscillator is connected to the OSC0 and OSC1 inputs, regardless of whether or not the MOSC is used or powered down.

This routine was last flash but had the PLLPWR enable bit in the wrong position and PYSDIV was set 4 not 3, both are corrected below. That N+1 is vague since the clock tree shows [4] and clock selection division tables. Perhaps don't show PHYSDIV already at 4 in tables then also state N+1 and show the same N+1 in register programming.  That method is highly confusing where N=3 not N=4 as is shown in the crystal frequency division and selection tables. 

	 /* Set the MOSC for High frequency oscillator */
	 HWREG(SYSCTL_MOSCCTL) |= SYSCTL_MOSC_HIGHFREQ;
	 /* When attached crystal clear PWRDWN and NOXTAL bits MOSCTL register*/
	 HWREG(SYSCTL_MOSCCTL) &= ~(SYSCTL_MOSC_PWR_DIS | SYSCTL_MOSC_NO_XTAL);
	 /* Wait until the MOSC indicates fully powered up */
	 while((!HWREG(SYSCTL_RIS) & SYSCTL_INT_MOSC_PUP))
	 {
	 }
	 /* Source OSCSRC[23:20] POR defaults PIOSC. */
	 HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_OSCSRC_MOSC;

	 /* When writing to PLLFRE0 Power down PLLPWR[23] */
	 HWREG(SYSCTL_PLLFREQ0) |= 0x00000000;
	 /* Set PLL MINT=96, MFRAC=0, PLLPWR=0 enable bits */
	 HWREG(SYSCTL_PLLFREQ0) |= 0x60;
	 /* Set PLL reduce jitter Q=0 and N=4  */
	 HWREG(SYSCTL_PLLFREQ1) |= (0x0 | 0x4);
	 /* Power up the PLLPWR[23] */
	 HWREG(SYSCTL_PLLFREQ0) |= 0x00100000;

	 /* Refresh Flash/EEROM speed  FWS/EWS[25:22]&[9:6]=0x5,
	  * FBCHT/EBCHT[19:16]&[3:0]=0x6 */
	 HWREG(SYSCTL_MEMTIM0) |= 0x01950195;
	 /* Check if TReady LOCK status */
     while(HWREG(SYSCTL_PLLSTAT) != 0x1)
     {
     }
	 /* Write the PSYSDIV PLL divisor N+1 [9:0]=0x3. */
	 HWREG(SYSCTL_RSCLKCFG) |=  0x3;

	 /* Enable MEMTIMU[31],NEWFREQ[30],USEPLL[28] Q0/Q1 Indicate to use 480Mhz PLL */
	 HWREG(SYSCTL_RSCLKCFG) |=
			 (SYSCTL_RSCLKCFG_MEMTIMU | SYSCTL_RSCLKCFG_NEWFREQ | SYSCTL_RSCLKCFG_USEPLL);

     /* Set MOSC is DeepSleep (DSOSCSRC) clock source */
	 HWREG(SYSCTL_DSCLKCFG) |= SYSCTL_RSCLKCFG_USEPLL;

BP101 said:

as any flash firmware updates DELL servers

One wonders if anyone else (EVER) would come to that conclusion?

The real ? is how did Unlock clear the user registers and flash and long believed the DAP? Seems the extra step is doing something more on the JTAG interface.

Many others this forum have been locked out and likely was doing the same procedure below.

Click on OK first informative message about holding reset need to power device. Then hold the MCU reset click OK to (unlock) click ok again then power cycle board. Power cycle in any device firmware update is always done last not first. Cisco, Dell, HP/Compaq, IBM and other industry leaders. Besides the message is vague and should say something more like:

"It is necessary to FIRST hold MCU reset button while power cycling the ICDI before clicking this OK button." LOL

On another note the launch pad has 2 USB ports to supply power and JP3 was set to OTG supplying power via USB hub. I had moved JP3 to ICDI position but wonder how the latter might effect the unlock procedure.