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ACP on the RM57L

eric
Intellectual 885 points
Other Parts Discussed in Thread: RM57L843

hi,

I got the information(as the following picture) from the cortex-r5 Trm.

I can see the RM57L contain a cortex-R5 core in it and it have several periphral that can be a external master e.g. the DMA, EMAC.

I need to know if the EMAC(as an external master) is connected to the ACP slave port? I met a coherency problem when read data that is writen(received) by the EMAC, but the read failed if I enable cache and succeed if disable cache.

  • 0
    TI__Guru**** 190806 points
    Hi Eric,
    Yes, EMAC will be an external master that will go through the ACP slave port. If EMAC writes something to the L2SRAM then the cache will be automatically invalidated. However, the uSCU is only operational if you configure the cache as write-through. The uSCU is not active when you are in write-back cache scheme.
  • 0 in reply to Charles Tsai
    Intellectual 885 points
    Hi Charles,
    I want to confirm that the cache will be automatically invalidated or kept updated when the EMAC writing something to the L2SRAM.
    if just invalidated, that means when CPU read the same memory, it still need to get data from L2SRAM not from cache if the memory is be cached in the cache.
    I feel that the uSCU+ACP will automatically keep the d-cache consistent with the L2SRAM when writen by EMAC. right?

    regards,
    Eric
  • 0 in reply to Charles Tsai
    Intellectual 885 points

    Hi Charles,

    I found if I want to use write-back policy, then I need to invalidate the cache line manually.

    I don't know how to invalidate the cache line, I found the following code from the code generated by the HAL. but this _dCacheInvalidate_ will invalidate the whole d-cache which will cause abort. can you show me how to invalidate several cache lines which are corresponding to the L2SRAM.

  • 0 in reply to eric
    TI__Guru**** 190806 points
    Hi Eric,
    I will suggest that you use write-through cache scheme to maintain data coherency. If you want to use write-back scheme then you can reconfigure the MPU such that the RAM area that is written by the EMAC is not cacheable or not shareable. This way when the EMAC writes data to the L2SRAM the CPU is required to read from the L2RAM to get the most current written data.

    To clean a few lines of cache is possible but you will need to know whether or not the old data is currently in the cache and where in cache the old data is located. This is not easy to find. I will not recommend this method of handling data coherency issue since there are other options which are viable to consider.
  • 0 in reply to Charles Tsai
    Intellectual 885 points

    Hi Charles,

    Can you show me the difference between the clean and invalidate operation for the cache? I am not clear about these two operations.

    The following screenshot is a cache operation from the cortex-M7, I think the cortex-R5(RM57L843) should also have the similar operations, right? if yes, can you show me the code (C or assembly both are ok for me)?

    I agree with your opinion, I will use the write-throughs scheme. one thing I am not sure is can I just configure a region as write-through and other as write-back to get the max performance.

    Another question I mentioned: the uSCU+ACP will keep the d-cache updated or just invalidate the corresponding d-cache lines when EMAC direct write L2SRAM with writh-through scheme?

  • 0 in reply to eric
    TI__Guru**** 190806 points

    Hi Eric,

      

    eric said:
    Can you show me the difference between the clean and invalidate operation for the cache? I am not clear about these two operations.

      Clean is to flush the contents in cache onto the L2 memory. This is only applicable in a write-back scheme as the cache contains the latest data while the L2 memory does not. Invalidate is just to mark the cache "not valid" so that CPU will not find a matching address in the cache and hence force the CPU to read from the L2 memory. 

    eric said:
    The following screenshot is a cache operation from the cortex-M7, I think the cortex-R5(RM57L843) should also have the similar operations, right? if yes, can you show me the code (C or assembly both are ok for me)?

    Below is an example code I got from ARM. Please consult with ARM if you have further questions. 

    ; ------------------------------------------------------------
; Assembler Function
; ------------------------------------------------------------

  PRESERVE8

Mode_USR          EQU   0x10
Mode_FIQ          EQU   0x11
Mode_IRQ          EQU   0x12
Mode_SVC          EQU   0x13
Mode_ABT          EQU   0x17
Mode_SYS          EQU   0x1F
Mode_SVP          EQU   0x13
Mode_UNDEF        EQU   0x1B
Mode_HYP          EQU   0x1A
Mode_MON          EQU   0x16

	AREA	STARTUPCODE,CODE,READONLY

	ENTRY

  EXPORT start
start
  NOP
  NOP
  NOP
  NOP
  MOV  r0, #0x80000
  MOV  r1, #0x1000
  BL   cleanInvalidateDCacheRange
  NOP
  NOP
  NOP
  LDR  r0, =0x90001
  LDR  r1, =0x1001
  BL   cleanInvalidateDCacheRange
  NOP
  NOP
  NOP

  MOV   r0, #0x18 ; Code for exit
  SVC   0x123456
loop
  B     loop

; ------------------------------------------------------------

  EXPORT cleanInvalidateDCacheRange
  ; void cleanInvalidateDCacheRange(unsigned int start, unsigned int size_in_bytes)
cleanInvalidateDCacheRange PROC


  MRC    p15, 0, r12, c0, c0, 1     ; Read CTR (Cache Type Register)
  UBFX   r12, r12, #16, #4          ; Extract DMinLine, gives log2 of the number of words
  MOV    r3, #1
  MOV    r12, r3, LSL r12           ; Convert to words
  LSL    r12, r12, #2               ; Convert from words to bytes

  ; Calculate end address
  ADD    r1, r0, r1                 ; End (r1) = start (r0) + size (r1)
  ADD    r1, r1, r12                ; Adding 1 cache length, this is to handle missing the end of the required range
                                    ; This could (probably will) mean operating on a larger range than requested.  
                                    ; However, this is "safe" due to the operation being performed (clean + invalidate)

invalidateDCacheRange_loop
  MCR    p15, 0, r0, c7, c14, 1     ; DCCIMVAC (Clean and invalidate data or unified cache line by address to PoC)
  ADD    r0, r0, r12                ; Increment address by cache line length
  CMP    r0, r1                     ; Check for end of range
  BLS    invalidateDCacheRange_loop


  DSB                               ; Ensure completion

  BX     lr
  ENDP
  END

; ------------------------------------------------------------
; End of file
; ------------------------------------------------------------

    eric said:
    I agree with your opinion, I will use the write-throughs scheme. one thing I am not sure is can I just configure a region as write-through and other as write-back to get the max performance.

    Yes, you should be able to do that. You will need to partition the L2RAM into multple regions with write-through or write-back in different regions. 

    eric said:
    Another question I mentioned: the uSCU+ACP will keep the d-cache updated or just invalidate the corresponding d-cache lines when EMAC direct write L2SRAM with writh-through scheme?

    No, the uSCU+ACP will not keep the d-cache updated. It will only invalidate the corresponding d-cache lines when EMAC writes to the L2RAM. 

     

  • 0 in reply to Charles Tsai
    TI__Guru 68920 points
    There is a document ARM DEN 0042A ARM® Cortex®-R Series Version: 1.0 Programmer’s Guide
    that has a chapter on cache maintenance including example code.
  • 0 in reply to Anthony F. Seely
    Intellectual 885 points
    Hi Anthony,
    Thank you, the PG helps a lot.