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Error 1170 using XDS200 on TM4C123GH6PZ - Custom Board

Krispin Davies
Prodigy 30 points
Other Parts Discussed in Thread: TM4C123GH6PZ

I am using CCSV6 (version 6.2.0.00048 on Windows 10 - 64bit) to connect to a Tiva TM4C123GH6PZ microprocessor on a custom board. The board/processor have functioned correctly using a different PC in CCSV5.

Attempting to launch the target configuration independent of any project is successful, however I am unable to connect to the CORTEX_M4_0 core. When I attempt the connection, I receive an Error 1170 message (below). If I attempt to connect to the CS_DAP_0 debug core the connection is successful, however memory map is unable to display values (only displays question marks).

I have attempted:

- Power cycling the board,

- Rebooting the computer,

- Changing USB ports that the XDS200 is plugged in on (does not work on any of the 3 USB3.0 ports available),

- Reducing the TCLK frequency (initally 10.0MHz, then 1.0MHz, 100KHz, 50KHz).

Thank you in advance for any advice you can offer. :)

The error message reads:

Error connecting to the target:
(Error -1170 @ 0x0)
Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK).
(Emulation package 6.0.407.3)

The results of the JTAG connection test all pass:

[Start: Texas Instruments XDS2xx USB Debug Probe]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\AIRSHO~1\AppData\Local\TEXASI~1\
CCS\ti\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'xds2xxu.out'.
The library build date was 'Jul 27 2016'.
The library build time was '17:54:51'.
The library package version is '6.0.407.3'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '13' (0x0000000d).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

This emulator does not create a reset log-file.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS2xx USB Debug Probe]

The confugration's CCXML file is as follows:

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Texas Instruments XDS2xx USB Debug Probe" href="connections/TIXDS2XXUSB_Connection.xml" id="Texas Instruments XDS2xx USB Debug Probe" xml="TIXDS2XXUSB_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS2xx USB Debug Probe">
<instance XML_version="1.2" href="drivers/tixds560cs_dap.xml" id="drivers" xml="tixds560cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds560cortexM.xml" id="drivers" xml="tixds560cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="0" id="The JTAG TCLK Frequency (MHz)">
<choice Name="Fixed with user specified faster value" value="SPECIFIC">
<property Type="stringfield" Value="10.0MHz" id="-- Enter a value from 0.5MHz to 20.0MHz"/>
</choice>
<choice Name="Adaptive with user specified limit" value="ADAPTIVE">
<property Type="stringfield" Value="10.0MHz" id="-- Enter a value from 0.5MHz to 20.0MHz"/>
</choice>
</property>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="Tiva TM4C123GH6PZ" href="devices/tm4c123gh6pz.xml" id="Tiva TM4C123GH6PZ" xml="tm4c123gh6pz.xml" xmlpath="devices"/>
<device HW_revision="1" XML_version="1.2" description="" id="Tiva TM4C123GH6PZ" partnum="TM4C123GH6PZ" simulation="no">
<router HW_revision="1.0" XML_version="1.2" description="CS_DAP Router" id="CS_DAP_0" isa="CS_DAP">
<subpath id="subpath_0">
<cpu HW_revision="1.0" XML_version="1.2" desc="CORTEX_M4_0" description="Cortex M4 CPU" deviceSim="false" id="CORTEX_M4_0" isa="CORTEX_M4"/>
</subpath>
</router>
</device>
</platform>
</connection>
</configuration>
</configurations>

  • 0
    TI__Guru**** 244400 points
    Hello Krispin,

    I would suggest first using the JTAG application note to isolate the issue.

    www.ti.com/.../spma075.pdf
  • 0 in reply to Amit Ashara
    Prodigy 30 points

    Thanks Amit,

    I have gone through all of the debugging steps now.

    Unlocking the processor seems to have partially addressed the problem. Following the unlock procedure, I can now sometimes connect to the CORTEX_M4_0 core when launching the target configuration independent of any project. The connection always fails on the first attempt to connect to the core, then succeeds approximately 25% of the time on successive attempts (not hitting the retry button, but cancelling and attempting to connect again). Using the memory browser, I can see memory values when connected.

    Attempting to load code onto the microprocessor still fails 100% of the time.

    In both cases, I am still receiving the same Error 1170 message as before.

    I have once again tested a range of TCLK speeds from 50 KHz to 10.0MHz.

    Cheers,

    Krispin

  • 0 in reply to Krispin Davies
    TI__Guru**** 244400 points
    Hello Krispin

    It seems that the program itself is then the cause of the issue. Are you locking JTAG debug using BOOTCFG, changing the GPIO for JTAG pins, mis-configuring the clock or using low power mode and then trying to connect?
  • 0 in reply to Amit Ashara
    Prodigy 30 points

    I think I may have given you the wrong impression Amit,

    The connectivity issues in my previous post are immediately following the unlock procedure. It's my understanding that the unlock procedure should restore the processor to factory defaults, so no code should be loaded onto the processor. Is this correct?

    Best wishes,

    Krispin

  • 0 in reply to Krispin Davies
    TI__Guru**** 244400 points
    Hello Krispin,

    Can you please share the schematics of your design, so that I can check if there are no board issues?
  • 0 in reply to Amit Ashara
    Intellectual 555 points
    Hi Amit

    I am working with Krispin on this project.
    I can send you a schematic for the design; I don't want to issue it to the forum; is there a separate email or FTP site I can use to get you a schematic?

    I would also like to provide some history for the board Krispin is using.
    Due to a layout error, the VDDC pins on the controller were connected to VDD.
    On Krispin's board, this was fixed prior to power up, and the VDD and VDDC measure correctly 3.3V and 1.2V respectively.
    For the modification, I replaced the capacitor on pin 86 with a 4.7uF X5R capacitor.
    This meets the capacitance recommendation in the TM4C123GH6PZ data sheet, but I don't think it will meet the ESR/ESL requirements.
    Is it possible to recommend a capacitor suitable for the VDDC rail?
    Krispin and I have scoped the VDDC pin, we did not see any noise or ripple.

    I have examined the JTAG application report (SPMA075) that you sent to Krispin.
    I noted the following differences between my schematic and the recommendations:
    1) Using 100k pullups where 10k is recommended.
    2) I used pullups on TDK, TMS, TDI and TDO; I note that TDO is recommended to be a pulldown, and no resistor for TDI.
    3) I have a 14 pin, 0.100" header. Therefore, there is no RESET pin, only the TRST pin. I tied TRST to the MCU RST pin 63. From what I see in the guide, this should be left open.
    Would you expect any of these 3 issues as a possible cause of our communications error?

    Thank you

    Dale
  • 0 in reply to Dale Tardiff
    TI__Guru**** 244400 points
    Hello Dale

    You can send it via the Forum Messenger. I have sent you a request. Once you accept it, you can send an off-forum message attaching the schematics.

    1. As for the cut out of the traces, i would need to see if the layout follows the guidelines as per the System Design Guidelines for routing the VDDC traces. i have never had an issue with the TM4C123x and TM4C129x when using the System Design Guidelines Application Note for TM4C12x devices
    2. You have to ensure that the total capacitance is between 2.5-4.5 uF. Do you need exact part numbers?
    3. The JTAG header is a 14 pin header. Are you using the CTI header map?
  • 0 in reply to Amit Ashara
    Intellectual 555 points
    Hi Amit

    I have sent the schematic for your reference.
    The capacitance is 3.3 uF. I selected this following the guidelines in Table 24-12 of the TM4C123GH6PZ data sheet.
    My concern was that a typical commercially available ceramic capacitor may not meet the ESR requirement (10 - 100 mohms).
    At this time, I believe it is more useful to correct my JTAG connections, and then examine the VDDC rail again if the problem is not solved.
    I am using the TI 14 pin map, as shown in Figure 5 of "Using TM4C12x Devices Over JTAG Interface". However, as you will notice on the schematic, I used pull up resistors for all 4 signals; therefore, I plan to correct my JTAG interface to match Figure 5.

    Thank you

    Dale
  • 0 in reply to Dale Tardiff
    TI__Guru**** 244400 points
    Hello Dale

    I checked the schematic and besides the obvious VDDC connected to VDD (which must be corrected in the schematic for future revision), the issue seems to be with the JTAG interface. As I pointed out in my first reply, to check the JTAG application note, the 14-pin header has one major issue. I.e. RTCK has been connected to the TCK being supplied from the JTAG debug probe. The TCK from the debug probe needs to be connected to Pin-11 of the header. What you may try is to short Pin-9 and Pin-11 of the header.
  • 0 in reply to Amit Ashara
    Intellectual 555 points

    Hi Amit


    I shorted pin 9 and pin 11 together.

    However, to get communications to work, I also noticed that pin 2 on the 14 pin header should be open; on my board this was connected to RST on Tiva.

    Opening this circuit allowed us to load code into the TM4C123GH6PZ.

    We have some issues with RTOS now; I will open a new thread if needed to examine these.

    Thank you

    Dale

  • 0 in reply to Dale Tardiff
    TI__Guru**** 244400 points
    Hello Dale

    Even the changes to Pin-2 and Pin-14 are mentioned in the JTAG application note.