Hi,
I configured 2 GPIOs from Port E as output. I can set and clear 1 GPIO, whereas the other one doesn't work as expected. (P0, P1)
My config is as follows
//DC-PE0 , RST-PE1
HWREG(GPIO_PORTE_AHB_BASE + GPIO_O_DIR) |= 0x00000003;
HWREG(GPIO_PORTE_AHB_BASE + GPIO_O_AFSEL) |= 0x00000000;
HWREG(GPIO_PORTE_AHB_BASE + GPIO_O_PC) |= 0x00000000;
HWREG(GPIO_PORTE_AHB_BASE + GPIO_O_DR2R) |= 0x00000003;
HWREG(GPIO_PORTE_AHB_BASE + GPIO_O_PUR) |= 0x00000003;
HWREG(GPIO_PORTE_AHB_BASE + GPIO_O_ODR) |= 0x00000003;
HWREG(GPIO_PORTE_AHB_BASE + GPIO_O_DEN) |= 0x00000003;
And I use the following Macro to Set/ clear GPIOs.
ROM_GPIOPinWrite (GPIO_PORTE_AHB_BASE , GPIO_INT_PIN_0,1);
ROM_GPIOPinWrite (GPIO_PORTE_AHB_BASE , GPIO_INT_PIN_1, 1);
I enabled the port clock RCGC register.
The issue I'm facing is that I'm not able to set PE1 Pin. I tried toggling using HWREG(Base_addr + gpio_dat) |= 0x00000002; still no improvment.
I tried inserting delays between write access.
The only way I'm able to set PE1 is by manually accessing the register and modifying through debug window. The Adjacent pin PE0 works completely normal.
And there is no special consideration for the pins that I mentioned.
Also I noticed in disassembly that each pin access has around 6-8 instructions, any way to access with less cloc cycles?
