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Questions about the Data sheet of TMS570LS3137-EP

Other Parts Discussed in Thread: TMS570LS3137-EP

I am reading "TMS570LS3137-EP 16- and 32-Bit RISC Flash Microcontroller (Literature Number: SPNS230D)".

About "Table 6-36. ESM Channel Assignments", I want to know the details.

I want to know the safety function or diagnosis to generate a following ERROR SOURCES.

[ERROR SOURCES]

-----------------------------------------------------------------------------------

DMA - imprecise read error

FMC - correctable error: bus1 and bus2 interfaces

DMA - imprecise write error

FMC - correctable error (EEPROM bank access)

FMC - uncorrectable error (EEPROM bank access)

IOMM - Mux configuration error

Ethernet Controller master interface

FMC - uncorrectable error (address parity on bus1 accesses)

RAM even bank (B0TCM) - uncorrectable error

RAM odd bank (B1TCM) - uncorrectable error

RAM even bank (B0TCM) - ECC uncorrectable error

RAM odd bank (B1TCM) - ECC uncorrectable error

FMC - uncorrectable error: bus1 and bus2 interfaces

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From the "Table 4. Summary of Safety Features and Diagnostics" of the Safety Manual, please tell me the Unique Identifier which generates the above error.

  • For details see the Technical Reference Manual SPNU499

  • Hi Bob Crosby

    I've read the Technical Reference Manual SPNU499.
    Please tell me about not understand of part.

    Please tell me the difference between "RAM even bank (B0TCM) - uncorrectable error" and "RAM even bank (B0TCM) - ECC uncorrectable erro".
    Please tell me the difference between "RAM odd bank (B1TCM) - uncorrectable error" and "RRAM odd bank (B1TCM) - ECC uncorrectable error".
    The diagnosis function which generates the respective errors, please answer.
  • Section 6.1.1 of the TRM SPNU499 has a diagram showing the two tightly coupled memory (TCM) interfaces used for RAM. B0TCM interfaces to 64 bits of RAM (plus 8 ECC bits) with the first address 0x8000000. It is called the even BTCM bus. B1TCM interfaces to 64 bits of RAM (plus 8 ECC bits with the first address 0x80000008. It is called the odd BTCM bus. The RAM addresses alternate between the two BTCMs every 8 bytes. Each BTCM has its own ECC logic and the errors are reported separately.

  • Hi Bob Crosby

    I was understanding about the differences between odd and even.
    But, my question can not be resolved.

    I want to know the difference between "RAM even bank (B0TCM) - uncorrectable error" and "RAM even bank (B0TCM) - ECC uncorrectable error".
    I want to know the difference between "RAM odd bank (B1TCM) - uncorrectable error" and "RRAM odd bank (B1TCM) - ECC uncorrectable error".

    In Figure 6-1, it has four "32 bits data and 4 ECC bits".
    For example, the error of the "Upper 32 bits data and 4 ECC bits" of Even side refers to the "RAM even bank (B0TCM) -uncorrectable error".
    For example, the error of the "Lower 32 bits data and 4 ECC bits" of Even side refers to the "RAM even bank (B0TCM) -ECC uncorrectable error".
    Is my understanding correct?
  • Haggy,

    The information you are looking for is in the TRM section 6.19 (Reset / Abort / Error Sources) Table 6-37:

    ERROR SOURCE  SYSTEM MODE ERROR RESPONSE  ESM HOOKUP group.channel
    B0 TCM (even) ECC single error (correctable)  User/Privilege  ESM  1.26
    B0 TCM (even) ECC double error (non-correctable)  User/Privilege  Abort (CPU), ESM => nERROR 3.3
    B0 TCM (even) uncorrectable error (i.e. redundant address decode) User/Privilege  ESM => NMI => nERROR  2.6
    B0 TCM (even) address bus parity error User/Privilege  ESM => NMI => nERROR  2.1

    The TCM RAM Wrapper performance some diagnostics like the redundant address decode a error detected in this logic is considered to be an uncorrectable error. This feature is described in the TRM section 6.3.3 (Redundant Address Decode).

    Best Regards,
    Christian