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cortex-r5 default access permission

eric
Intellectual 885 points

Hi,

How does the default access permission look like after reset? I know the core run in the supervisor mode and is in privilege mode. I means the access to the SRAM and EMIF space. What about if I change into user mode? (I can find the default memory map and the attribute, but can not find the access right description in the cortex-r5 TRM)

How does the access permission look like if I just enable the background MPU? (for privilege and for un-privilege)

  • 0
    TI__Guru 72500 points

    Table 7-1 on page 7-2 of the Cortex R5 TRM shows the default memory protection.

  • 0 in reply to Bob Crosby
    TI__Guru 72500 points
    After re-reading your question, I realized I did not answer it. Certain registers in the peripheral space can only be written in a privileged mode. Those registers are identified in the device TRM from TI. Once you change to user mode, a write to a privileged register will cause an abort.
  • 0 in reply to Bob Crosby
    Intellectual 885 points

    Hi Bob,

    I know that some registers in the peripheral and in the core space can only be written in a privileged mode. I want to know what about the RAM space if I just enable the background MPU? (for the privileged mode and un-privileged mode)

    If I disable the MPU(including the background) does that mean the privilege and un-privilege can access the RAM space without generating an abort? (I know that certain registers access still be in the privileged mode)