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Regarding the Data abort due to 2-bit SRAM ECC error

Sreekanth Reddy Challa
Expert 1320 points
Other Parts Discussed in Thread: TMS570LS0332

Hi,

I am using TMS570LS0332 in my design and i also ported SafetyTI lib to the micro controller. I am getting the data abort when even i run the the following SRAM self test function.

SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM);

I have the following quires.  Please let me know your comments.

1. If 2bit ecc fault occurs in SRAM, will group 2 esm interrupts (Channel 6 and Channel 8) trigger? I do not get interrupts.  (I am in debug mode running with XDS200 emulator)

2. If the interrupts does not occur, should i handle the error in data abort exception?

Thanks & best Regards,

Sreekanth challa

  • 0
    TI__Guru 68950 points
    So you are entering the abort handler?

    Abort is a higher priority than IRQ / FIQ and will disable the IRQ/FIQ on entry.

    Do you have anything other than a while(1) in the abort handler?

    FYI regarding debug normally I,F are disabled while single stepping, but not while 'running' even running to a breakpoint. Although you can control this behaivor w. a setting in CCS.
  • 0 in reply to Anthony F. Seely
    Expert 1320 points

    Hi Anthony,

    As i have mentioned, i have ported the SafeTI libraray to TMS570LS0332. I am using the data abort function provided by in exception_handlers.c file of SafeTI library.

    As per my understanding, the data abort exception only takes care of SRAM_ECC_2BIT_FAULT_INJECT test. It calls the ESMapplication call back. 

    Thanks & Best Regards,

    Sreekanth reddy challa