Other Parts Discussed in Thread: HALCOGEN
Hello,
i'm have currently implemented RTI interrupt ticks on my own without using HALCoGen.
RTICLK is set to 75MHz, the FRC is updated every 1 sec by 1.
The compare register is set to 1 and the updated compare register is also set to 1, to generate an interrupt every 1sec.
Below you can see the implementation of the ISR:
#pragma CODE_STATE(RTI_COMPARE0_ISR, 32)
#pragma INTERRUPT(RTI_COMPARE0_ISR, IRQ)
void RTI_COMPARE0_ISR() {
// clear INT0 compare match interrupt flag
while (rtiREG1->INTFLAG & 0x00000001)
rtiREG1->INTFLAG = 0x00000001;
RTI_comp0_counter++;
}
In the main loop i cyclically compare the counter value to the previous one which is incremented by 1 with every interrupt, but only if i wait until the INTFLAG has been cleared. If i remove the while loop, the interrupt is called twice unless i do an a sufficient amount of operations are performed in the ISR.
Is this behaviour normal due to internal delays or might there be an error in the implementation somewhere else?
Thanks a lot in advance.
Kind regards,
Sebastian
