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PWMnCTRL REG 12-15, MINFLTPER and LATCH bits and ADC digital comparator mandate

Genatco
Guru 55913 points
Other Parts Discussed in Thread: TM4C1294NCPDT

Seems the word (either) is missing in datasheet context of ADC digital comparator fault source operation.

Perhaps the intended message infers a need to set either LATCH or MINFLTPER 1 when ADC digital comparator is an included fault source not both?

Why set MINFLTPER bit 17 if or when LATCH bit 18 is set ?... does the LATCH bit over rule the need for any delay timer (MINFLTPER) as notes suggest?

LATCH:

Note: When using an ADC digital comparator as a fault source, the

LATCH and MINFLTPER bits in the PWMnCTL register should

be set to 1 to ensure trigger assertions are captured.

  • 0
    TI__Mastermind 22580 points
    Hello BP101,

    Which TM4C device are you referring?

    Thanks,
    Sai
  • 0 in reply to Sai Reddy
    Guru 55913 points

    Hi Sai,

    Seems that got lost in my post: TM4C1294NCPDT. 

    BTW the M0nFaults are triggering and latching with only the LATCH bit now set each generator. Still wonder about ADC digital comparator if it has some odd condition that makes it necessary for MINPER bit to be set even when LATCH bit is already set. 

    Seems to me that setting the MINPER bit 1 would not be required if the digital comparator fault is being latched. 

    Thank you :)

  • 0 in reply to Genatco
    Guru 55913 points

    BTW: Oddly table 27-62 mentions the timing of (TfltTmax=40ns) time up to inactive PWM state, this case 60Mhz PWM clock. The M0nFault timing is extremely fast from outside in but not so much asserted from generator errors inside out and mainly dead band generator assertions relative to DBCTRL enable times! 

    There are no useful timing diagrams for the different dead band modes relative to PWM control block drives listed in the electrical characteristics. So we only have results of scope captures to design circuits by or use trial error methods. Can a company sign non disclosure to get zoom view circuit analysis of PWM fault handling and dead band timing diagrams of the PWM peripheral?