To use for what the memory address?

Hello Arrly,

 What it is saying in the safety manual is that the uncorrectable ECC error address is recorded in the CPU's  Data Fault Address Register. When the CPU detects an uncorrectable ECC error it will automatically take a data abort exception. You can find out the cause of the data abort exception by reading the Data Fault Status Register. Please go to section 4.2.18 Fault Status and Address Registers in the Cortex-R4F TRM for details. Below is an excerpt.

I understood, Uncorrectable ECC error address is recorded in the CPU's Data Fault Address Register.

Uncorrectable ECC error address which recorded in the CPU's Data Fault Address Register is how to use ?
For what is it record the error address?

Best Regards.
Arriy

Your question is not clear to me. You want to know how to use the ECC error address recorded in the DFAR? Normally in a real application you should not get any ECC error unless there is some real fault detected for the memories. The error address tell you which address is causing the CPU to abort. The error address can be in either in the flash memory or SRAM. If an error address is from the SRAM then it is most likely a transient fault. You can re-read the same address to see if you will get an ECC error again. If you re-read the same address from SRAM and it still gives you an ECC error then it is a permanent fault. Same for the flash memory. The flash memory will not have transient fault unless the fault is due to the flash controller logic. For un-correctable ECC faults and being permanent, I think your application will want to go to the safe mode. The ESM nERROR is asserted for such type of error.

Hi Charles.

ECC error is detected, the address recorded in DFAR registers, performs ECC again using the recorded address.
And,it is a permanent failure If find the error, it is a transient failure If not find the error ? Right ?

I might have to say that not clear ,
Is there a possibility ECC 3bit error is detected as correctable 1bit error ?

Also, do I need to distinguish between the data failure or address decoder failure ?

Hi Arriy,
The implemented ECC circuit is SECDED (Single Error Correct Double Error Detect). The SECDED has no capability to reliably detect any errors which are 3-bit or higher. Therefore, if you truly have a 3-bit error then the SECDEC may detect it as a single bit error, a double bit error or even no error at all. The SECDED has limitation to detect up to 2 bits only and nothing more.

I don't think you need to distinguish between data failure or address decoder failure. Inside the flash memory there are flash memory bits and the address decoder logic such as row and column decodes and multiplexing and sense amp. If any one part of these components is bad then you most likely will read wrong data anyway. In Hercules devices such as TMS570LS31x the ECC is generated not for just the data but also the address. So if you have an address error it will be detected as well.

Hello Arriy,
Is your question answered? If your question is answered can you please click the 'Verify Answer' button to close the thread? Thanks.

Hi Charles,

I'm reading "TMS570LS3137-EP 16- and 32-Bit RISC Flash Microcontroller(Literature Number: SPNS230D)".


Charles said "I don't think you need to distinguish between data failure or address decoder failure. " is means possible to distinguish between data failure or address decoder failure from ERROR SOURCE ? (I see the "Table 6-37. Reset/Abort/Error Sources" )

In the SRAM, I think "B0 TCM (even) ECC single error (correctable)" and "B0 TCM (even) ECC double error (non-correctable)" are data failure,"B0 TCM (even) uncorrectable error (i.e. redundant address decode)" and "B0 TCM (even) address bus parity error" are address decoder failure. Right ?

Hi Arriy,
Earlier I thought you were asking if you need to distinguish between the data error and the address decoder error in the flash memory. This is why I said this is not necessary. The reason is that for flash memory the ECC is generated based on both the data and the address.

Now you re asking for the SRAM. This will be different. The ECC for the SRAM is only protecting the data. So the address is not protected. Yes, for SRAM, you will need to distinguish between data failure and address failure. The TCRAMW can detect parity error on the address and control bus. In addition, there is internal built-in redundant address decoder. These two type of additional diagnostics are meant for the address diagnostic.

Hi Charles.
Thank you your answer.

I understand need to distingish between data failure and address failure.
But I don'k know how to do.

Where it has been described ?