Performance Monitoring Unit (PMU) is Threshold for overflow

Arriy

Other Parts Discussed in Thread: HALCOGEN, SYSBIOS

I'm reading "Chapter 6" of "Cortex™-R4 and Cortex-R4F (Revision: r1p4)".

I have a question about "Performance Monitoring Unit (PMU)".

This docments explains PMU is "you can enable or disable each of the event counters individually,and read and reset the overflow flag for each counter."

Overflow Flag Status Register(PMOVSR) to flag is set , when the each of the three counters detects a number of events?

Threshold to become an overflow is can be set by the user ?

over 9 years ago

0 Chester Gillon over 9 years ago

Guru 92251 points

Arriy said:
Threshold to become an overflow is can be set by the user ?

The operation of the Performance Monitoring Unit (PMU) registers is defined by the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition ARM DDI 0406C.c (ID051414).

The events are counted in 32-bit wrapping counters, which overflow when they wrap from 0xffffffff to 0x0. While there is no mechanism to directly set the threshold at which an overflow occurs, section C12.3.1 Generating overflow interrupt requests of the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R contains the following:

Software can write to the counters to control the frequency at which interrupt requests occur. For example, software might set a counter to 0xFFFF0000, to generate another counter overflow after 65536 increments, and reset it to this value every time an overflow interrupt occurs.

i.e. the software can set the initial value of an event counter to be non-zero to control how many events are counted before the next overflow interrupt occurs.

0 Charles Tsai over 9 years ago in reply to Chester Gillon

TI__Guru**** 191886 points

Thanks Chester for the clarification.

0 Arriy over 9 years ago in reply to Chester Gillon

Expert 1720 points

The software can set the initial value of an event counter is which register ?
Do I set the initial value in the "6.3.9 c9, Event Count Registers"(PMXEVCNTR) ?

0 Chester Gillon over 9 years ago in reply to Arriy

Guru 92251 points

Arriy said:
Do I set the initial value in the "6.3.9 c9, Event Count Registers"(PMXEVCNTR) ?

Yes, that is my understanding.

As of HALCoGen v04.05.02 there isn't a PMU function to write to an Event Count Register, so you will have to write your own function.

0 Charles Tsai over 9 years ago in reply to Arriy

TI__Guru**** 191886 points

Please go to sys_pmu.asm for all the available API. If you want to initiate the event or cycle counter to zero you can use use the below API.

;-------------------------------------------------------------------------------
; Reset Cycle Counter

    .def     _pmuResetCycleCounter_
    .asmfunc

_pmuResetCycleCounter_

        stmfd sp!, {r0}
        mrc   p15, #0, r0, c9, c12, #0 
        orr   r0,  r0, #4
        mcr   p15, #0, r0, c9, c12, #0
        ldmfd sp!, {r0}		
        bx    lr

    .endasmfunc

;-------------------------------------------------------------------------------
; Reset Event Counters [0..2]

    .def     _pmuResetEventCounters_
    .asmfunc

_pmuResetEventCounters_

        stmfd sp!, {r0}
        mrc   p15, #0, r0, c9, c12, #0 
        orr   r0,  r0, #2
        mcr   p15, #0, r0, c9, c12, #0
        ldmfd sp!, {r0}		
        bx    lr

    .endasmfunc

;-------------------------------------------------------------------------------
; Reset Cycle Counter abd Event Counters [0..2]

    .def     _pmuResetCounters_
    .asmfunc

_pmuResetCounters_

        stmfd sp!, {r0}
        mrc   p15, #0, r0, c9, c12, #0 
        orr   r0,  r0, #6
        mcr   p15, #0, r0, c9, c12, #0
        ldmfd sp!, {r0}		
        bx    lr

    .endasmfunc

0 Vladimir Romanov over 9 years ago

Intellectual 940 points

Do you want use PMU to get 64-bit cycle count?

0 Arriy over 9 years ago in reply to Vladimir Romanov

Expert 1720 points

It is not yet decided.
For change threshold by use bits of the counter ?

0 Vladimir Romanov over 9 years ago in reply to Arriy

Intellectual 940 points

IMHO RTI is better. RTI has 32 bit overflow register. This is my code. By default RTI use RTI1CLK (80 mz).

void configureTimerForRunTimeStats (void) {
    if (timer_already_init) {
        return;
    }
    rtiInit ();
    rtiREG1->CNT [1U].CPUCx = 0;
    rtiStartCounter (1u);
    timer_already_init = true;
}

uint64_t getRunTimeCounterValue64 (void) {
    register uint32_t c1, c1_, c2;
    c1 = rtiREG1->CNT [1U].FRCx;
    c2 = rtiREG1->CNT [1U].UCx;
    c1_ = rtiREG1->CNT [1U].FRCx;
    if (c1_ != c1) {
        c1 = c1_;
        c2 = rtiREG1->CNT [1U].UCx;
    }
    return ((uint64_t) c1) << 32 | c2;
}

0 Chester Gillon over 9 years ago in reply to Vladimir Romanov

Guru 92251 points

Vladimir Romanov said:
IMHO RTI is better. RTI has 32 bit overflow register.

The PMU can count other events that just clock cycles.

I don't know if Arriy just needs a clock cycle count, in which case the RTI could be used instead, or if the PMU needs to be used for other events.

For the PMU events I have formed 64-bit counts by using the overflow interrupt to maintain a 32-bit overflow count in software.

[I haven't posted the example code since it was for a Cortex-A device using the SYS/BIOS ti.sysbios.family.arm.v7a.Pmu module]

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Performance Monitoring Unit (PMU) is Threshold for overflow