SafeTI library with speed optimizations in CCS

Hi Sreekanth,
Please find out the address that caused the FMC correctable error by going to the FCOR_ERR_ADD in the Flash Controller module. What address do you see? Once you know the address you might need to single step to the area of the disassembly code that accesses this location and try to understand the reason for the correctable error.

Dear Charles,

Thanks for your input. I followd the steps specified in your response. The address in the FCOR_ERR_ADD is not even in the memory range of my application. The address is pointing to bootloader code. This address is different on every reset.

But i observed the following.
1. This happens only once and i never get the interrupt.
2. This happens only when i have optimization: Speed Vs Size trade off is set to 5
3. The FCOR_ERR_ADD address is exactly 32 bytes ahead of the value of a global variable in my application.
Ex: FCOR_ERR_ADD = 0x3D28 and Global variable value = 0x3D48. This is very consistant.

Thanks & Best regards,
Sreekanth Challa

Hi Sreekanth,
Can you also read out the FEDACSTATUS register?

What optimization level do you have? According to the compiler userguide the --opt_for_speed=5 can have a high risk of worsening the code size. I think somehow the optimization may result with the CPU performing a speculative fetch from an unimplemented address that results in ECC error. I will suggest that you stay with --opt_for_speed=4 or lower.

Hi Chales,
We have --opt_for_speed=5.

The following flags in the FEDACSTATUS register are set.
1. ERR_ZERO_FLG
2. B1_UNC_ERR

I will try with the lower optimizations.

Thanks & Best regards,
Sreekanth challa