My target device is an RM44L520 running at 120 MHz with a VCLK4 = 60 MHz.
With the parameters shown below, VCLK4 should be divided by 20, to yield a 3 MHz time base clock.
Is Halcogen in error, is the TRM (spnu608) wrong, or have I made some other error?
Halcogen screen shot:
Relevant section from Tech Ref Manual (section 17.4.1, page 684).
12-10 CLKDIV R/W 0h Time-base Clock Prescale Bits. These bits determine part of the
time-base clock prescale value.
TBCLK = VCLK4 / (HSPCLKDIV x CLKDIV)
0h = /1 (default on reset)
1h = /2
2h = /4
3h = /8
4h = /16
5h = /32
6h = /64
7h = /128
9-7 HSPCLKDIV R/W 1h High Speed Time-base Clock Prescale Bits. These bits determine
part of the time-base clock prescale value.
TBCLK = VCLK4 / (HSPCLKDIV x CLKDIV)
0h = /1
1h = /2 (default on reset)
2h = /4
3h = /6
4h = /8
5h = /10
6h = /12
7h = /14
