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Limitation of EPI

Massa1
Expert 1065 points
Other Parts Discussed in Thread: TM4C1294NCPDT

Hi there, please teach me how to design a system.

We are designing a system with TM4C1294NCPDT using EPI.
In the data-sheet, we found a limitation of frequency of EPI.
In Table 11-2, when we employ Memory configurations with 2 chip selects, the maximum performance is 40MHz.
Does 40MHz mean maximum clock frequency?
We can't find the explanation about memory configurations in the electrical characteristics in chapter 27.15.
Please tell me why the limitation is 40MHz or 20MHz.
We want to know the basis in the electrical characteristics.

Thanks

Massa

  • 0
    TI__Guru**** 244400 points
    Hello Massa,

    This is because of the loading of the EPI IO's due to two connected device load, that there is a limitation of the maximum clock frequency. As the load increases the timing in terms of rise and fall time may change. This can limit the maximum operating frequency.
  • 0 in reply to Amit Ashara
    Expert 1065 points
    Hello, Amit Ashara.
    Thank you for your quick reply.

    I understand the limitation is depend on the number of loads.
    We will design the circuit to work EPI under the maximum frequency.
    Thanks, again.

    Regards,

    Massa
  • 0 in reply to Amit Ashara
    Guru 47900 points

    Amit Ashara said:
    As the load increases the timing in terms of rise and fall time may change.

    Back in "days of old" both address & data bus "buffers" were employed to insure fast rise/fall times - and prevent undue load upon the (far less capable) MCUs.   Might those prove useful here, too?

  • 0 in reply to cb1
    Guru 11940 points

    Back in "days of old" both address & data bus "buffers" were employed to insure fast rise/fall times - and prevent undue load upon the (far less capable) MCUs.

    But more often because of either fan-out constraints (current limitations) or multiplexed buses (data and address bus in different variations) of the processor.

    Anyway, using external memory for an MCU is always a crutch - they are designed to have those "internalized". The external bus interface of the TM4C (and other comparable Cortex M4 devices) has several limitations, compared to "real" microprocessors.

  • 0 in reply to cb1
    TI__Guru**** 244400 points
    Hello cb1

    They may but the user needs to verify that the functions on bi-directional buses are met by the use of the buffers and that the delay fits the timing budget.