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RM57 MPU Cache Settings - TEX, C and B encodings

Rik Anderson
Prodigy 110 points
Other Parts Discussed in Thread: HALCOGEN

On the RM57 (when TRE==0) I was wondering if the following cache settings are exactly the same (for the Internal RAM)?

TEX[2:0] = 001 C = 1, B = 1  which is defined as Outer and Inner Write-Back, Write-Allocate

compared to

TEX[2:0] = 101 C = 0, B =1  which is defined as Outer Write-Back, Write-Allocate, Inner Write-Back, Write-Allocate.

This is just one example. You seem to be able to define a lot of the same settings in two different ways, one with TEX[2] set to 0, the other with it set to 1 (See ARM-v7-R Architecture Reference Manual tables B3-10 & B3-11). I would like to know on the RM57 if it makes any difference which method you use or if they are freely interchangeable (exactly equivalent) ?

Would one method be recommended over the other? I suspect it makes no difference on the RM57, however I assume one method is more likely to be forward compatible with future products.

Thanks,

Rik

  • 0
    TI__Guru**** 191906 points
    Hi Rik,
    There is no L2 cache in RM57 so the outer policy is irrelevant to the RM57.

    The TEX[2:0] = 001 C = 1, B = 1 and TEX[2:0] = 101 C = 0, B =1 will produce identical behavior. The 2nd method allows you to define different cache policy in either inner or the outer cache. The first method with the TEX[2]=0 only allows you to apply the same cache policy on both the inner and outer cache. Again, what is defined for the outer policy is irrelevant for RM57.

    If you use HalCoGen to setup the MPU, it does not have selections to choose different policy for inner or outer cache.