The basic problem is that we get FMC ECC errors on new units loaded with our software. We are only using Bank 0, Sectors 0-4. I'm guessing the errors are due to speculative reads by the processor into the sectors 5-14 and have confirmed by seeing that the double-error address stored in the FMC registers is in this range. We are able to make these errors go away if we flash the unit with a build that includes explicit fills of all these sectors. Our actual application is bootloadable, so we would like to keep our release hex files to a minimal size.
Assumptions:
1. The ECC tables are not populated on a virgin chip.
2. Doing a full flash erase invalidates the ECC tables and they are not re-written unless specifically programming the empty sectors with 0xFF fill and auto-ECC enabled.
Are these assumptions correct? Is there a way to avoid or correct this issue without having to release one build for bootloading that only includes the active sectors and another 4MB build for flashing virgin parts to setup the unused sectors? Of course, if there were a way to turn off the speculative reads in the core, this would probably correct the problem as well, but I didn't see such a setting.
Thanks,
Jeff