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Primary SRAM BTCM Address and Control Bus Parity

Arriy
Expert 1720 points

I am reading "Safety Manual for TMS570LS31x and TMS570LS21 x Hercules ARMR-Based Safety Critical Microcontrollers (Literature Number: SPNU511D)".

"Detected errors are signaled to the ESM by the SRAM and the error address is captured in the SRAM wrapper." in chapter "7.99 Primary SRAM BTCM Address and Control Bus Parity"

The error address captured in the SRAM wrapper,this address how to use ?

I think,performs parity again using the recorded address.

And,it is a permanent failure If find the error, it is a transient failure If not find the error,right?

BestRegards,

Arriy.

  • 0
    TI__Guru**** 190476 points

    HI Arriy,

    Arriy said:
    And,it is a permanent failure If find the error, it is a transient failure If not find the error,right?

    your understanding is correct.

     This is a parity error on the address bus and control signals, not data. You can re-read from the same address again to see if a parity error is still there. The parity error address is stored in the RAMPERRADDR register. You can also perform a diagnostic of the parity logic by using the ADDR PARITY OVERRIDE bit in the RAMCTRL register. By setting the ADDR PARITY OVERRIDE bit to 0xD you are forcing the RAM wrapper to perform an opposite parity scheme. It will create parity error and you can use this scheme as a diagnostic to see if the parity logic is truly functioning.

    .