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Hello,
I'm a new to the Hercules Launchpads.I wrote a small code to test the ability of the RTI to generate a time base and I'm currently facing a predicament of
an unknown origin.
The RTI generates a compare0 interrupt,as indicated by RTIINTFLAG register (bit 0 is 1), but, apparently, the VIM doesn't handle it .
I've cleared the IRQ bit from CPSR, enabled the channel 2 interrupt from REQENASET0 (in VIM) and enabled the interrupt in RTISETINTENA (RTI).
I'd like to mention that I've made a similar program concerning GIO interrupts ,the only difference was the channel and, of course, enabling the interrupt in the
appropriate GIO register.
I've also used rtiInit() to rule out potential initialization erros.
Would you kindly provide some advice regarding the cause of this ?
[CODE BEGIN]__________________________________
#include "HL_sys_common.h" #include "HL_RTI.h" #define rti_base 0xFFFFFC00 #define RTIGCTRL ((volatile uint32 *)rti_base) #define RTITBCTRL ((volatile uint32 *)(rti_base + 0x04)) #define RTICOMPCTRL ((volatile uint32 *)(rti_base +0x0C)) #define RTIFRC0 ((volatile uint32 *)(rti_base +0x10)) #define RTIUC0 ((volatile uint32 *)(rti_base +0x14)) #define RTICPUC0 ((volatile uint32 *)(rti_base +0x18)) #define RTICOMP0 ((volatile uint32 *)(rti_base +0x50)) #define RTIUDCP0 ((volatile uint32 *)(rti_base +0x54)) #define RTISETINTENA ((volatile uint32 *)(rti_base +0x80)) #define RTIINTFLAG ((volatile uint32 *)(rti_base +0x88)) #define RTIINTCLRENABLE ((volatile uint32 *)(rti_base +0xAC)) #define vim_base 0xFFFFFE00 #define IRQINDEX ((volatile uint32 *)(vim_base)) #define FIRQPR0 ((volatile uint32 *)(vim_base+ 0x10)) #define INTREQ0 ((volatile uint32 *)(vim_base+ 0x20)) #define REQENASET0 ((volatile uint32 *)(vim_base+ 0x30)) #define IRQVECREG ((volatile uint32 *)(vim_base+ 0x70)) #define CHANCTRL2 (((volatile uint32 *)(vim_base + 0x80)) #define CHNADDR2 ((volatile uint32 *) (0xFFF8200C)) void THIS_ISR(); volatile uint32 x=0; volatile uint32 value=0x1000; void main(void) { //-----------------------------------VIM asm(" MRS R1, CPSR "); // asm(" BIC R1, R1 ,#0x80 "); // ENABLE IRQ asm(" MSR cpsr_c, r1 "); // *FIRQPR0 &=(uint32) 0xFFFFFFFB; *REQENASET0 |=(uint32) 0x04; *CHNADDR2 =(uint32) (& THIS_ISR); //-----------------------------------RTI rtiInit(); *RTIGCTRL =(uint32) 0x10000; *RTITBCTRL =(uint32) 0; *RTICOMPCTRL |=(uint32) 0x1110; *RTICPUC0 =(uint32) value; *RTIUDCP0=(uint32) 0x40000; *RTICOMP0=(uint32) 0x40000; *RTISETINTENA |=(uint32) 0x100; *RTIINTCLRENABLE &=(uint32) ~(0x01); *RTIGCTRL |=(uint32) 1; } void THIS_ISR(){ x++; asm(" MRS R1, CPSR "); asm(" BIC R1, R1 ,#0x80 "); asm(" MSR cpsr_c, r1 "); } [CODE END]____________________________________________
Thank you for your time!
Hello,
Thank you for the advice. I will try to tackle this predicament by employing the use of HalCoGen's framework.