TM4C129 auto MDI/MDIX sample_timer issue

Tim Meyer29

I currently have a TM4C129 microcontroller in a product and am using the internal ethernet PHY with the auto-negotiate and auto-MDI/MDIX enabled. Currently the product is being tested for compliance for auto-MDI/MDIX at an outside lab. The lab has reported that the sample_timer used with the Linear Feedback Shift Register to determine the length of time and on which channel to transmit the Fast Link Pulses has a value on the MDI channel of 526ms and 62ms on the MDIX channel. The max allowed value per the IEEE spec is 64ms. What could cause the timing for the MDI channel to be so far off?

over 9 years ago

0 Amit Ashara over 9 years ago

TI__Guru**** 244440 points

Hello Tim,

TM4C129x has passed UNH testing on the Integrated PHY. So I am not sure why the issue is coming.

Tim Meyer29 said:
Fast Link Pulses has a value on the MDI channel of 526ms and 62ms on the MDIX channel. The max allowed value per the IEEE spec is 64ms.

Was the 62 ms specified a typo?

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

Thank you for your response. Yes, the 62ms was a typo and should have been 64ms. It must be something in our implementation. Going back over the schematic, it appears that the RBIAS resistor was unfortunately omitted. Is it possible that this could cause the bad behavior of the PHY?

Tim Meyer

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

One other thought, could you provide me with the code and the schematic of the board you used for the UNH testing? This may help us to narrow down what the issue is on our side.

Thank you again!

Tim Meyer

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim,

Ouch (sorry for the unprofessional use of the word), but RBIAS is mandatory....

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

Yeah, we are in the process of correcting this. RBIAS aside, could our code be causing this issue, or are all bets off at this point?

Tim Meyer

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim

I don;t think your code is causing this and I believe at this point it is the RBIAS. The Auto MDI/MDIX is controlled as enable by the software without having to program a timer.

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

It looks like the RBIAS was added in the last revision of the board, so it is installed in the device that is failing the auto-crossover test. Any other ideas?

Thank you!

Tim Meyer

Electrical Engineer

tim.meyer@telect.com

22425 Appleway Ave. #11

Liberty Lake WA 99019

telect.com

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim

I would now check the crystal stability, layout and PCB construction-trace impedance.

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

The crystal appears to be stable and at the correct frequency. The FLPs appear to be correct looking at the signal on the cable. The FLP clock pulses are spaced 128us apart (64us between clock and data pulses) and the burst frequency is 16ms.

Tim Meyer

Electrical Engineer

tim.meyer@telect.com

22425 Appleway Ave. #11

Liberty Lake WA 99019

telect.com

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim

Which crystal are you using (Datasheet or link to it), so that I can double check. Also the second point is about the layout of the traces themselves and the PCB construction, trace width, etc.

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

The part is:

Abracon ABM8G-25.000MHZ-18-D2Y-T

http://www.abracon.com/Resonators/ABM8G.pdf

Tim Meyer

Electrical Engineer

tim.meyer@telect.com

22425 Appleway Ave. #11

Liberty Lake WA 99019

telect.com

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim

The crystal selected has an ESR of 60 Ohms which is out of spec for the max ESR of 50 Ohms for 25MHz crystal.

I am still awaiting the layout information that has been requested.

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

Here is the Crystal layout (Crystal highlighted gray on right)

Tim Meyer

Electrical Engineer

tim.meyer@telect.com

22425 Appleway Ave. #11

Liberty Lake WA 99019

telect.com

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim,

The Ethernet RX and TX layout and PCB construction, not the crystal. Though the Crystal layout is not as per the System design guidelines Application Note

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

Out of curiosity, how does the TX and RX trace layout cause the PHY to continue transmitting FLPs on the MDI channel for longer than the max allowed by the auto-crossover specification?

Tim Meyer

Electrical Engineer

tim.meyer@telect.com

22425 Appleway Ave. #11

Liberty Lake WA 99019

telect.com

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim

I want to first eliminate the obvious. I have seen issues where connectivity breaks due to improper design rules and layout and in almost all cases it has been the layout correction that effects the end result.

0 Tim Meyer29 over 9 years ago

Prodigy 130 points

Amit,

Thank you for the clarification.

The RX lines go to the bottom layer and to pins 14 and 12 of the connector. I had only the top layer highlighted in the screen capture.

Tim Meyer

Electrical Engineer

tim.meyer@telect.com

22425 Appleway Ave. #11

Liberty Lake WA 99019

telect.com

0 Amit Ashara over 9 years ago in reply to Tim Meyer29

TI__Guru**** 244440 points

Hello Tim

I believe you are using Altium Designer. I would need to see first the construction of the PCB signal and power layers, the manufacturing process information so that I can check if the 100 ohm Impedance requirement for Ethernet is being met. Then I would be checking the trace layout for both RX and TX.