Unable to properly read from FPGA using EMIF DMA

Hi Andy,
Is this the LC4357 device?

Sorry, I have to ask a few questions to narrow down the problem area.

1. You said that from logic analyzer you can see all the reads (960 of them) performed. Is this true? I want to isolate problem area between EMIF and DMA. If the reads by EMIF is proper then we can focus on the DMA, i.e. the datapath from EMIF->Interconnect->DMA_FIFO->Interconnect->L2 SRAM and from L2SRAM->Cache->CPU.

2. What are the values in the so called 'holes'? Are they just zeros or some random values?
3. Is it true that if you only have one active DMA channel and you will still see 'holes' in the destination buffer?

Below are some experiments that I'd like you to try.

1. You said the holes are multiple of 32 bytes. Even though the DMA FIFO is 32-bytes the cache line is also 32 bytes. I don't think the problem is due to the FIFO. You declared the EMIF as a device-shareable region. But you didn't say how you configure the MPU setting for these buffers? Are you in write-back cache scheme? If you are in write-back cache scheme can you change to write-through? Or as a experiment, if you have the cache enabled can you simply disable it and see if it makes a difference. If you have write-back cache scheme then what is written by the DMA to the buffer will not be seen by the CPU if these buffer addresses are already stored in the cache tag address memory.

2. If the above experiment does not make any differences then you can play with #2 experiment. Can you first initialize the holes in the buffer with some known values? After the DMA is triggered I want to know if these pre-initialized values are overwritten with new values or they stay the same. This helps me to know if the DMA skipping the transfers or not.

Charles,

 I disabled the cache and it all started working . I had already done the experiments so I can tell you (and anyone else who may urn across this post) :

1: We only had one DMA access. We alternate on two channels but only one can be active at a time. This allows us to process the buffers in 'slow time'. The logic analyzer showed that all 960 reads were performed and that the data that was placed in RAM (as opposed to the holes)  was in the right place (i.e.  the correct offset from the start of the block).

2: I filled the buffer with 'A5's and they stayed there so the holes were areas where no write occurred rather than areas where zero was written.

3 : I tried changing the cache to write-through but it made no difference.

Thanks for the fast response and good advice. We will leave cache turned off.