Hello,
I have just upgraded HALCoGen from 4.05.02 to 4.06.00 and CCS to 6.1.2.00015. I changed nothing to my HALCoGen file and to my code. Regenerated files from HALCoGen and recompiled. Got one comiplation error and everything works except the SDRAM on the EMIF.
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Compile error is caused by line 186 in emif.c:
/* prevents optimization */
buffer = buffer;
I had to comment it out.
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Malfunction of the SDRAM comes from line 195 in emif.c:
/* Place the EMIF in Self Refresh Mode For Clock Change */
/* Must only write to the upper byte of the SDCR to avoid */
/* a second intiialization sequence */
/* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */
*((unsigned char *)(&emifREG->SDCR) + 0x0U) = 0x80;
Being low endian, this line writes to the LSB instead of the MSB, therefore overwriting from 4 banks to 1 bank! I comment it out and now works.
I have no problem commenting theses lines out, the problem is every time I regenerate files from HALCoGen, I must not forget to re-comment out. Even if I re-write the proper data in the following USER section, that command re-issue an SDRAM initialization sequence...
Even if this line was properly done (offset +0x3U instead of +0x0U --> MSB), I found no call where the SDRAM comes out of self-refresh.
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Furthermore, at line 166 of emif.c, a 32 bit value (8000005 --> 0x7A1205) is written in SDRCR, field RR is limited to 13 bits. And I have no clue how this value is calculated
/* Procedure B Step 3: Program the RR Field of SDRCR to provide 200us of initialization time */
emifREG->SDRCR = 8000005U;
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Lastly, I understand that these changes are driven from EMIF#5 errata, but the latest errata document stops at EMIF#4.
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Could you please provide information on what I am doing wrong, workarounds or please let me know when these bugs are fixed.
Regards,
Hugues
