Flash Wrapper Address ECC

Hi Haggy,
The ECC is encoded for both the data and the address at the same time. There is no separate enable/disable for the address ECC. For example, you have a 64-bit data at address location 0x100. The ECC is generated for the combination of the 64-bit data and the address 0x100. Now suppose the CPU wants to read from address 0x100 and let's suppose the flash memory has defect and read from location 0x200 instead. The 64-bit data from location 0x200 in combination with the expected address 0x100 would have resulted in a different ECC that the CPU will detect as a fault.

So a fault in address is no different than a fault in data. The ESM GP3.7 will be set.

Hi Charles,

I have created the following program. However, ESM GP3.7 does not occur.
ESM GP1.36 has occurred.
Please tell me the wrong part.

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uint32 ecc;

/* Set Single Error Correction Threshold as 1 */
flashWREG->EECTRL2 |= 1U;

/* Enable EEPROM Emulation Error Profiling */
flashWREG->EECTRL1 |= 0x00000100U;

/* Load FEMU_XX regs in order to generate ECC */
flashWREG->FEMUADDR = 0xF0200000U;
flashWREG->FEMUDMSW = 0U;
flashWREG->FEMUDLSW = 0U;

/* ECC for the correct data*/
ecc = flashWREG->FEMUECC;

/* Load data with address&data bit error */
flashWREG->FEMUADDR = 0xF0200100U;
flashWREG->FEMUDMSW = 1U;
flashWREG->FEMUDLSW = 0U;

/* Enable Diagnostic ECC data correction mode and select FEE SECDED for diagnostic testing */
flashWREG->FDIAGCTRL = 0x00055001U;

flashWREG->FEMUECC = ecc;

/* Diagnostic trigger */
flashWREG->FDIAGCTRL |= 0x01000000U;
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Hi Haggy,
You are testing the diagnostic mode 1. The diagnostic mode 1 is for ECC diagnostic on the bus2. The flash wrapper has two buses, the bus1 and bus2. The bus1 is used by the CPU to access the flash's normal sectors for which the program and data are stored. The CPU will use the bus2 to access the OTP sectors, EEprom emulation flash bank. When CPU accesses via bus1 for the program and data, the CPU's built-in SECDED logic will perform the ECC checking. Note this ECC logic is inside the CPU, not inside the flash wrapper. When CPU accesses via bus2 for the EEprom bank or the OTP sectors the ECC checking is done inside the flash wrapper. The reason is that the CPU's level 2 interface (AXI-M bus) which is connected to the flash memory system's bus2 does not have ECC checking capability. Therefore, the flash wrapper has its own ECC logic just for bus2 accesses.


The flag in the ESM is GP1.36 which is FMC - uncorrectable error (EEPROM bank access). This is the correct error flag when testing diagnostic mode 1. If you want to test the ECC inside the CPU you will need to use diagnostic mode 7.

Please also refer to the TRM on the Bus1 Diagnostic Mode Summary and Bus2 ECC Diagnostic Mode Summary. You will find that for Bus1 Diagnostic the mode 1 is not applicable. The mode 1 is only applicable for bus2.

Hi Charles,
I am confused.
Take a look at Table 4. Summary of Safety Features and Diagnostics of Safety Manual for TMS570LS31 (SPNU511D).
Diagnosis of FEE7 (Flash Wrapper Address ECC) is the Diag Mode 4 from Diag Mode 1.
Please tell me how to set the ESM GP3.7 of your answer.

If the Diag Mode 1 in GP1.36 has been set, do you have succeeded the fault injection of FEE7 (Flash Wrapper Address ECC)?

Hi Haggy,

 As I said you need to use Diagnostic mode 7 to test the ECC logic inside the CPU. Please see below instructions from the TRM.

5.6.2.6 ECC Data Correction Diagnostic Mode 7: DIAGMODE = 7

Testing the error correction and ECC logic in the CPU involves corrupting the ECC value returned to the

CPU. By inverting one or more bits of the ECC, the CPU will detect errors in a selected data or ECC bit, or

in any possible value returned by the ECC.

To set an error for a particular bit use the syndrome, see Table 5-3. For instance if you want to corrupt

data bit 62 then put the value 70h into the test register.

The method uses the DATA_INV_PAR value in the FPAR_OVR register to alter the ECC during a slave

access cycle. The value in the DATA_INV_PAR register will be XORed with the current ECC to give a bad

ECC value to the CPU. This only will occur when the DIAG_MODE is 7, the PAR_OVR_KEY is 5, the

DIAG_EN_KEY in the FDIAGCTRL register is 5 and the access is a slave cycle.

This mode can set the FEDACSTATUS status error bits ECC_MUL_ERR or ERR_ZERO_FLG but it will

not set D_UNC_ERR nor D_COR_ERR. Also the logic to support the ECCx_MAL_ERR and

COMx_MAL_GOOD bits is not implemented for the CPU path so these bits will not set.

The sequence to do this test would be:

1. Make sure the true DMA module is off.

2. Put 0101b into PAR_OVR_KEY and 101b into DAT_INV_PAR fields (00005Axxh) of the FPAR_OVR

register (0x7C).

3. Put the desired value in DAT_INV_PAR field of FPAR_OVR register.

4. Put 7 in DIAG_MODE, and 5 in DIAG_EN_KEY of FDIAGCTRL (0x6C).

5. Do a slave access of the desired address.

6. Put 0 in DIAG_MODE or A in one of the key fields to turn off this test.

7. Check error registers for ECC errors. (0x14, 0x1C, 0x20).

8. Repeat as necessary to test out the ECC.

9. Put 0 in DIAG_MODE and A in both of the key fields to completely disable this test at the end of the

test.

10. Write 5400h to FPAR_OVR(0x7C) to clear DAT_INV_PAR and put 2 into PAR_OVR_KEY.

If you use HalCoGen then check the API checkFlashECC() in the sys_selftest.c. This API implements the diagnostic mode 7.

Hi Charles,
Thank you for support.
For my question method is bad, I think that confuses you.
I want to organize the discussion.

I use the diagnosis of "Flash Wrapper Address ECC" to Flash EEPROM Emulation.
I will monitor the ESM flag for detecting an error in the "Flash Wrapper Address ECC".
Therefore, please tell me all the ESM flag generated by the error of "Flash Wrapper Address ECC".