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eQEP module software reset

Szilard Lovas
Expert 1425 points
Other Parts Discussed in Thread: TMS320F28035

Hi Guys,
I'm dealing with eQEP interface. The A,B and I pin is connected to the resolver circuit's (AD2S1210) emulated encoder output.
I set up "Position counter reset on the first index event" (0x2 to QEPCTL[13:12]), but it behaves like "Position counter reset on the maximum position" manner.
It turned up, that AD2S1210 generates encoder pulses after its reset. It could be the cause of this phenomena and of course I could make a workaround for several ways, but is there any way to soft reset eQEP peripherial?

Regards, Szilárd

ps: An addition: First index marker flag (FIMF QEPSTS[2]) always zero.

  • 0
    TI__Guru**** 191886 points

    Hi Szilard,

     There is no separate software reset for eQEP.

     Are you in forward movement or reverse movement?

     I read below in the TRM and just wondering if this could be the reason.

    34.2.2.3.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)

    If the index event occurs during forward movement, then the position counter is reset to 0 on the next eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to the value in the QPOSMAX register on the next eQEP clock

  • 0 in reply to Charles Tsai
    Expert 1425 points
    Hi Charles,
    I'm going to check it on the next week. Thank You, and have a nice weekend (and Halloween maybe).
    Regards, Szilárd
  • 0 in reply to Charles Tsai
    Expert 1425 points

    Hi Charles,

    I just kept reading spnu563.pdf and checking what happens after reset.

    According to page 1926, the default values of COEF, CDEF and FIMF bits are '1'.

    But after the reset, I can read out all zero values of QEP registers.

    I also feel inconsistency about this row:

    FIMF First index marker flag:
    - 0 Sticky bit, cleared by writing 1
    - 1 Set by first occurrence of index pulse

    If it's after reset default value is 1 how could it signal, that a first index pulse has arrived? So I don't really understand.

    As I see the eQEP IP comes from c2000 and SPRUFK8 contains word-for-word same information.

    What do yo think about it?

    Regards, Szilárd

  • 0 in reply to Szilard Lovas
    TI__Guru**** 191886 points
    Hi Szilard,
    I checked across several TRMs from Hercules devices to C2000 devices and they all have the reset value of 1 for FIMF. I also checked RM57x and RM46x silicon and they both show a value of 0 after reset on the bench. So I don't really know whether it is a TRM inconsistency issue or there is some underlying problem. Since the module IP came from C2000 I will need to look for their expert on this module.
  • 0 in reply to Charles Tsai
    Expert 1425 points

    Hi Charles,

    I have checked the QEPSTS after reset value on a piccolo TMS320F28035 device with same result:

    spnu563 page page 1895 (34.2.2.1 eQEP Memory Map) also says that the reset values are all zero.

    But, still not not understand, how first index detect method should works. I've never seen FIMF as '1', although writing it seemingly do something.

    Regards, Szilárd

  • 0 in reply to Szilard Lovas
    TI__Guru**** 191886 points
    Hi Szilárd,
    I'm trying to contact the person who knows eQEP in C2000 but the person is out of office until Nov-14. Since you can reproduce the issue in piccolo device I will suggest that you separately raise the question in C2000 forum and hopefully you can get a faster closure on the issue.
  • 0 in reply to Charles Tsai
    Expert 1425 points

    Hi Charles,
    Thank you for your effort! I'm going make a workaround until the eQEP expert arrives.

    Just for a short summary:
    - The documentation seems to be inconsistent (spnu563 page 1895 ⇔ 1926).
    - On the page 1926: UPEVNT should be R/W-1 or R/W-0 (not R-1).
    - The hardware issue (or feature :)) of eQEP module.
    Regards, Szilárd

  • 0 in reply to Charles Tsai
    Expert 1425 points

    Hi Charles,

    Could you take a glimpse on this?

    What is your opinion?

    Regards, Szilárd

  • 0 in reply to Szilard Lovas
    Expert 1425 points
    Hi Charles,
    As I see, there is a problem, with updating register values.
    In spite of "Continuous refresh" is enabled, the CCS refresh the register values when I suspend the running.
    FIMF is set by the first index signal and I can clear it by writing 1, but after that never arise again.
    I don't know if is the normal functionality, but (at least) looks close to it.
    Regards, Szilárd
  • 0 in reply to Szilard Lovas
    TI__Guru**** 191886 points
    Hmm, interesting. So the register window and the memory window are displaying different values?

    What about other registers like QFLAG? Are they matching between register and memory window?

    Can you use the DAP to read the memory?