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Tivaware SysCtlClockFreqSet cpu clock

Hi,

I am using TM4C129, TI RTOS. In my code I use log_write1 to get the duration of some code execution.

When I configure the cpuFreq on cfg file for 120MHz I get a duration of 6850ns. When I configure it to 16MHz I get a 51375ns duration. This is fine.

Here is the problem:

When I keep the cpuFreq on cfg file in 120MHz and on my code I use the SysCtlClockFreqSet function to also set the system clock to 120Mhz I also get a 6850ns duration. But, when I use the SysCtlClockFreqSet function to set the system clock to 16MHz I get a 4000ns duration!!!

What is happenning? Are the cpuFreq and the System Clock different things? How come a lower frequency achieves a bigger duration?

Thanks,

Paulo

  • Hello Paulo

    SysCtlClockFreqSet is the API for setting the system clock in TivaWare. When you call the function what are the values of the register of RSCLKCFG, MEMTIM0, LLFREQ0, PLLFREQ1 set as?
  • RSCLKCFG: 0x03000003
    MEMTIM0: 0x00300030
    PLLFREQ0: 0x00000060
    PLLFREQ1: 00000004
  • Hello Paulo

    The register values are correct for a 16MHz clock. Where are you measuring the 4000ns period?
  • Paulo Freitas de Araujo Filho said:
    When I keep the cpuFreq on cfg file in 120MHz and on my code I use the SysCtlClockFreqSet function to also set the system clock to 120Mhz I also get a 6850ns duration. But, when I use the SysCtlClockFreqSet function to set the system clock to 16MHz I get a 4000ns duration!!!

    The "CPU clock frequency (Hz)" set in the TI-RTOS cfg file is the *assumed" CPU frequency which SYS/BIOS uses for converting between CPU cycles and actual time. If the *assumed" CPU frequency set in the TI-RTOS cfg file doesn't match the actual target CPU frequency then the time measured reported by SYS/BIOS will be incorrect.

    When you use the SysCtlClockFreqSet function to change from 120MHz and 16MHz what I thinks happens is the actual number of CPU cycles requires reduces because at 16MHz flash wait states aren't required, but because TI-RTOS has been told the CPU frequency is still 120MHz which leads to an incorrect duration being reported.

    i.e. try changing the frequency set by the SysCtlClockFreqSet  and the "CPU clock frequency (Hz)" set in the TI-RTOS cfg file to the same value.

  • The 4000ns is time measurement of a function on my code. I am getting it using two Log_write1 statements and the duration analysis from System Analyser.
    The thing is, when I don't use the SysCtlClockFreqSet function to set the clock to 16MHz and set the cpuFreq to 16MHz instead using the cfg file the time measured is 51000ns.
  • Here are the measurements I am taking:

    cpuFreq on cfg file SysCtlClockFreqSet inside main code time measured with log_write1
    120MHz - 6800ns
    120MHz 120MHz 6800ns
    120MHz 16MHz 4000ns
    16MHz 16MHz 35000ns
    16MHz - 51000ns

    What is happenning? What is the actual frequency of the board? What is the correct time measured?

    Thanks,
    Paulo

  • Paulo Freitas de Araujo Filho said:
    What is the correct time measured?

    My belief is that the following combinations give the correct time measured, since the actual frequency of the CPU and the assumed frequency used in the System Analyzer match:

    cpuFreq on cfg file SysCtlClockFreqSet inside main code time measured with log_write1
    120MHz 120MHz 6800ns
    16MHz 16MHz 35000ns

    One way to confirm the correct time measurement would to also toggle a GPIO pin around the code being measured, and use a LSA or oscilloscope to also externally measure the duration.

    The ratio of 120MHz / 16MHz is 7.5, yet the code with a CPU frequency of 120MHz is only 5.15 times faster than that with a CPU frequency of 16MHz. That may be explained by the effect of flash wait states when operating at a CPU frequency of 120MHz.

  • Hello Paulo

    The most certain method as Chester pointed out is to use a Timer with PWM output to see the divided clock.