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About exceptions

Haggy
Intellectual 440 points
Other Parts Discussed in Thread: TMS570LS3137-EP

I am using the TMS570LS3137-EP.
I want to know about the exception of ARM® Cortex ™-R4F.

I'm reading the reference manual  of Cortex™-R4 and Cortex-R4F(Revision: r1p3).

An exception is correct in the following content?
If there is a shortage, please tell me.

【Table 2-6 Exception vectors】

・Reset
・Undefined instruction
・Software interrupt
・Abort (prefetch)
・Abort (data)
・IRQ
・FIQ

【Table A-18 FPU signals】

・Masked floating-point inexact exception
・Masked floating-point overflow exception
・Masked floating-point underflow exception
・Masked floating-point invalid operation exception
・Masked floating-point divide-by-zero exception
・Masked floating-point input denormal exception

I want to know vector of floating-point exception.

Please tell me the reference page of the manual.

  • 0
    TI__Guru 72500 points
    Section 12.5.3 of the Cortex R4 TRM r1p3 documents that the FPU does not support user-mode traps. However, TI has taken the 6 output signals from the FPU described in this section and then put them through an OR gate. The output of that OR gate can generate an interrupt on VIM channel 47.
  • 0 in reply to Bob Crosby
    Intellectual 440 points
    Hi Bob,
    I have additional questions.
    Look at the Safety Manual for TMS570LS31 (SPNU511D).
    To "7.7 CPU Illegal Operation and Instruction Trapping" There is a Privilege violation. Does this support the trap?
    Also, Privilege or violation is located where the description of the manual?
  • 0 in reply to Haggy
    TI__Guru 72500 points

    The illegal instructions trap at address 0x00000004. A privilege violation will generate a data abort and trap at address 0x00000010. A privilege violation is when a register is accessed in USER mode when it is only supposed to be accessed in a privileged mode. The peripheral register bits that reqiure privileged access are documented in the device TRM. For example, writing to the clock source disable register (CSDIS  page 131) in USER mode would cause a data abort. Reads in USER mode are allowed.

  • 0 in reply to Bob Crosby
    Intellectual 440 points
    Hi Bob,

    I've read Section 12.5.3 of the Cortex R4 TRM r1p3.
    I can not understand the meaning of "The FPU does not support user-mode traps".
    In the case of privileged mode, FPU Is possible to support the trap?
    Please tell me the meaning of "The FPU does not support user-mode traps".
  • 0 in reply to Haggy
    TI__Guru 72500 points
    The FPU does not directly support traps in user mode or privileged modes. (I am not sure why ARM chose the words "The FPU does not support user-mode traps".) As described above TI has added a way on the Hercules devices to generate an interrupt on an FPU exception.