eFuse controller - Any bit set in the error status register

Enable "EFUSE Self test" in HALCoGen. The test is then initiated in the routine efcSelfTest() in the file sys_selftest and the flag is verified in the routine checkefcSelfTest() from the same file.

I run "efcSelfTest" generate by HALCoGen.

But,not set ESM error flag is Group1,Channel40.
Do you know Why ?

I want to answer this question.
Please answer.

Arriy,

I think this may be a repeat question - see e2e.ti.com/.../2008245

Hi,Anthony.

Sorry I'm lack of confirmation.

I execute "Stuck at Zero Test" and "efcSelfTest" generate by HalCoGen.
So ESM error flag "Group1 Channel41" and "Group3 Channel1" are set , but "Group1 Channel40" is not set.

I want to execute fault injection test for eFuse ECC.
I think that the ECC test will be completed by setting the ESM "Group1 Channel40" flag.

Can be considered ECC fault injection test is completed by execute "Stuck at Zero Test" and "efcSelfTest" ?

Arriy,

Doesn't that pretty much match up with what is supposed to happen for the self test in the column of the table below that I put the arrow on?

Hi,Anthony.

Thank you your described.

I want to Group1 Channel40 flag is set by fault injection test. what do I do ?
I executed "eFuse Self Test", but flag is not set....

Arriy,

I would do as you said, and execute eFuse Self Test. According to the table that should set channel 40 so probably something is wrong in the procedure.