LBIST STC fault injection

Yes, it is done by the function stcSelfCheck(). Make sure you enable the "CCM Self test" in HALCoGen so that you have the necessary call and handling in the sys_startup.c file.

Thank you your answer.

I enable "CCM Self test", and  step Into run "stcSelfCheck()" in sys_selftest.c , generate by HALCoGen.
But,Group1 Channel 27 is not set.

Right the following code?

void stcSelfCheck(void)
{
/* USER CODE BEGIN (8) */
/* USER CODE END */
    volatile uint32 i = 0U;

    /* Run a diagnostic check on the CPU self-test controller */
    /* First set up the STC clock divider as STC is only supported up to 90MHz */

    /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */
    systemREG2->STCCLKDIV = 0x01000000U;

    /* Select one test interval, restart self-test next time, 0x00010001 */
    stcREG->STCGCR0 = 0x00010001U;

    /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */
    stcREG->STCSCSCR = 0x1AU;

    /* Maximum time-out period */
    stcREG->STCTPR = 0xFFFFFFFFU;

    /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
 /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
 /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
    for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }

    /* Enable self-test */
    stcREG->STCGCR1 = 0xAU;

/* USER CODE BEGIN (9) */
/* USER CODE END */

    /* Idle the CPU so that the self-test can start */
    _gotoCPUIdle_();

/* USER CODE BEGIN (10) */
/* USER CODE END */
}

Without error and into " _gotoCPUIdle_();"

Error not occur is right behavior ?

Do you know how to error occur ?

I want to answer this question.
Please answer.

I think you don't understand the mechanism here Arriy.

This line doesn't begin the CPU self test:

   /* Enable self-test */

   stcREG->STCGCR1 = 0xAU;

It enables it,  but the self test doesn't begin until the CPU executes a WFI instruction

(enters the idle state).   Which is what happens inside:   _gotoCPUIdle_();

And the exit from self test is through a CPU reset, so this function call doesn't return.

Now, this particular code you are looking at is tricky to execute even with the debugger.

That is because WFI is a 'hint' instruction it is not guaranteed to put the CPU into IDLE.  
That means the STC may or may not start the first time that the WFI is executed.

There are many conditions including debug requests and any interrupt requests to the CPU  (EVEN if the I AND F bits of CPSR have the interrupts disabled!)  that keep the CPU from entering IDLE and prevent the self test from beginning.

And when you do get the self test to execute - you come out at the reset vector again.

*and* when you run the self test - the breakpoint you might have set at the reset vector is cleared because that breakpoint lives inside the CPU logic that is tested.  [the CPU state isn't restored automatically so the breakpoint is gone after the STC runs.].

So if you want to observe this through the debugger you really need to write some code that checks for a CPU reset and puts you into some delay loop where you actually have enough time to halt the device execution...   You can't even set a HW breakpoint at address 0 to trap the reset.

Hi Anthony.
I have misunderstanding LBIST exective timing.

As usual ESM error flag "Group1 Channel27" is not set by execute "_gotoCPUIdle_();" in "stcSelfCheck()".

But after executed "stcSelfCheck()", "Self-Test Fail Status Register (STCFSTAT)" and
"Self-Test Global Status Register (STCGSTAT)"is set 0x00000003.(Error occued)

Described as "In case of a MISR mismatch or a test timeout, an error is generated through the ESM module." in "TMS570LS3137EP_TechnicalReferenceManual(SPNU499B)".

Why is not notified to ESM ?

I want to answer this question.
Please answer.

How are you making this observation?

"As usual ESM error flag "Group1 Channel27" is not set by execute "_gotoCPUIdle_();" in "stcSelfCheck()"."

This is actually difficult to observe correctly because after executing this test, the CPU is reset and breakpoints are erased so you would need to make sure you have done something to stop the CPU in a while(1) loop or some similar construct, before it re-runs the device initialization which may in fact clear the flag that you are trying to observe.

Hi,Anthony.
Thank you your answer.

I understand "As usual ESM error flag "Group1 Channel27" is not set by execute "_gotoCPUIdle_();" in "stcSelfCheck()"."

Is there another way to achieve fault insertion to LBIST ?
This means ESM error flag Group1 Channel27 is set.

I think I don't really understand the question.

Did you happen to look at the SafeTI Diagnostic Library.
It implements a fault-injection option for the STC if you call SL_SelfTest_STC with test type STC_COMPARE_SELFCHECK.
And there is another API to get you the status.

Hi Anthony.

Thank you your answer.

I got what I wanted to do, after executed "SL_SelfTest_STC" of SafeTI Diagnostic Library.

You said "LBIST selftest finished is through a CPU reset".

But after selftest , System Exception Status Register(SYSESR) flag is not set.

Do you know why ?