Hi,
I am Trying to use ADC + DMA Combination in TMS570LC4357
I have configured to convert 18 channels and once 18 conversion is done
DMA should transfer 18 results to the RAM Buffer in SRAM.
I am not able to See any transfer happening.
Whether any configuration i have missed ?
ADC Config
/** - Reset ADC module */
adcREG1->RSTCR = 1U;
adcREG1->RSTCR = 0U;
/** - Enable 12-BIT ADC */
adcREG1->OPMODECR |= 0x80000000U;
/** - Setup prescaler */
adcREG1->CLOCKCR = 31U; //adcREG1->CLOCKCR = 2U;
/** - Setup memory boundaries */
adcREG1->BNDCR = (uint32) (((uint32)0<<16) | ((uint32)(9)));
adcREG1->BNDEND = 2;
/** - Setup event group conversion mode
* - Setup data format
* - Enable/Disable channel id in conversion result
* - Enable/Disable continuous conversion
*/
adcREG1->GxMODECR[0U] = (uint32)ADC_12_BIT
| (uint32)0x00000000U
| (uint32)0x00000000U;
/** - Setup event group hardware trigger
* - Setup hardware trigger edge
* - Setup hardware trigger source
*/
adcREG1->EVSRC = (uint32)0x00000000U
| (uint32)ADC1_EVENT;
/** - Setup event group sample window */
adcREG1->EVSAMP = 5U;
/** - Setup event group sample discharge
* - Setup discharge prescaler
* - Enable/Disable discharge
*/
adcREG1->EVSAMPDISEN = (uint32)((uint32)0U << 8U)
| (uint32)0x00000000U;
/** - Setup group 1 conversion mode
* - Setup data format
* - Enable/Disable channel id in conversion result
* - Enable/Disable continuous conversion
*/
adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT
| (uint32)0x00000032U;
/** - Setup group 1 hardware trigger
* - Setup hardware trigger edge
* - Setup hardware trigger source
*/
adcREG1->G1SRC = (uint32)0x00000000U
| (uint32)ADC1_EVENT;
adcREG1->G1DMACR = 0x00120005;
/** - Setup group 1 sample window */
adcREG1->G1SAMP = 0U;
/** - Setup group 1 sample discharge
* - Setup discharge prescaler
* - Enable/Disable discharge
*/
adcREG1->G1SAMPDISEN = (uint32)((uint32)0U << 8U)
| (uint32)0x00000000U;
/** - Setup group 2 conversion mode
* - Setup data format
* - Enable/Disable channel id in conversion result
* - Enable/Disable continuous conversion
*/
adcREG1->GxMODECR[2U] = (uint32)ADC_12_BIT;
/** - Setup group 2 hardware trigger
* - Setup hardware trigger edge
* - Setup hardware trigger source
*/
adcREG1->G2SRC = (uint32)0x00000000U
| (uint32)ADC1_EVENT;
/** - Setup group 2 sample window */
adcREG1->G2SAMP = 5U;
/** - Setup group 2 sample discharge
* - Setup discharge prescaler
* - Enable/Disable discharge
*/
adcREG1->G2SAMPDISEN = (uint32)((uint32)0U << 8U)
| (uint32)0x00000000U;
/** - ADC1 EVT pin output value */
adcREG1->EVTOUT = 0U;
/** - ADC1 EVT pin direction */
adcREG1->EVTDIR = 0U;
/** - ADC1 EVT pin open drain enable */
adcREG1->EVTPDR = 0U;
/** - ADC1 EVT pin pullup / pulldown selection */
adcREG1->EVTPSEL = 1U;
/** - ADC1 EVT pin pullup / pulldown enable*/
adcREG1->EVTDIS = 1U;
/** - Enable ADC module */
adcREG1->OPMODECR |= 0x80140001U;
/** - Wait for buffer initialization complete */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while (((adcREG1->BNDEND & 0xFFFF0000U) >> 16U ) != 0U)
{
} /* Wait */
/** - Setup parity */
adcREG1->PARCR = 0x00000005U;
/** - Setup FiFo size */
adcREG1->GxINTCR[1] = 1;//s_adcFiFoSize[0][1];
/** - Start Conversion */
adcREG1->GxSEL[1] = M_AD1CHANNELS;
dma config
//
uint8 l_Index_u8;
dmaDisable();
DMA_CPClear();
dmaEnable();
g_dmactrladc_st.SADD = (0xFFF7C0B0);
for(l_Index_u8=0; l_Index_u8< 180;l_Index_u8++)
{
g_adcdatabuff_u32[l_Index_u8]=0x11111111;
}
g_dmactrladc_st.DADD = &g_adcdatabuff_u32;
g_dmactrladc_st.FRCNT = 1;
g_dmactrladc_st.ELCNT = 18;
g_dmactrladc_st.RDSIZE = ACCESS_32_BIT;
g_dmactrladc_st.WRSIZE = ACCESS_32_BIT;
g_dmactrladc_st.TTYPE = FRAME_TRANSFER;
g_dmactrladc_st.AUTOINIT = 1;
g_dmactrladc_st.ADDMODERD = ADDR_FIXED;
g_dmactrladc_st.ADDMODEWR = ADDR_INC1;
g_dmactrladc_st.CHCTRL = 0;
g_dmactrladc_st.ELDOFFSET = 0;
g_dmactrladc_st.ELSOFFSET =0;
g_dmactrladc_st.FRDOFFSET =0;
g_dmactrladc_st.FRSOFFSET =0;
g_dmactrladc_st.PORTASGN =PORTB_READ_PORTA_WRITE;
dmaSetCtrlPacket(DMA_CH0,g_dmactrladc_st);
dmaReqAssign(DMA_CH0, DMA_REQ7);
dmaSetChEnable(DMA_CH0, DMA_HW);
