Hello,
We currently have a design that uses the nERROR pin to automatically reset the processor when an ESM failure occur. We have used the nRST pin as we would like to be able to read registers at start-up in order to know what caused the reset. For the purpose of this discussion, we can assume that we have connected nERROR directly onto nRST.
Reading through the datasheet and the TRM, it is unclear to us how this pin behaves :
- While the processor is in reset (nRST) following an ESM failure
- While the processor is in reset (nRST) not following an ESM failure (e.g. watchdog holding this pin low)
- The reset state of the pin seems to be IPD 20uA, when is this pull down relied on ?
In order for our design to work, we would need the nERROR pin to go low and to recover high after a while in order to release the nRST line. If the pin goes low and never goes back up, then the processor will never recover an ESM failure.
Could you please advice if there is a way, in software, to program the behaviour of this pin such that it would output a low pulse when an ESM failure occur. This low pulse would be fed to the nRST pin so that the processor would reset itself.
Many thanks,
Laurent
