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About PCR Access Management

Haggy
Intellectual 440 points

I am reading the Safety Manual for TMS 570LS31x (SPNU 511D).

I have questions about the diagnosis of "Level 2 and Level 3 Interconnect".

I want to check error handling of "PCR Access Management".

Please tell me how to set up "PCR Access Management" for "Level 2 and Level 3 Interconnect".

And please tell me how to generate "PCR Access Management" error.

  • 0
    TI__Guru 68920 points

    Please refer to SPNU499 section 2.5.3 Peripheral Central Resource (PCR) Control Registers.

    This explains the registers that are available for access protection (Peripheral Memory Protection and Peripheral Protection Registers..)

    And also the clock gating function (Peripheral Memory Power Down and Peripheral Power Down) that SPNU511D talks about.

    The reporting is done through the standard abort exception of the CPU, please see 2.3.2.5 Conditions That Generate Aborts.

  • 0 in reply to Anthony F. Seely
    Intellectual 440 points
    Hi Anthony,

    I created the following program.
    But, an abort does not occur even if the SPI register is accessed.
    Please tell me the mistake.

    /* All peripheral/peripheral memory frames are out of reset */
    systemREG1->CLKCNTL |= 0x00000100U;

    /* - Protection set to all peripherals */
    pcrREG->PPROTSET0 = 0xFFFFFFFFU;
    pcrREG->PPROTSET1 = 0xFFFFFFFFU;
    pcrREG->PPROTSET2 = 0xFFFFFFFFU;
    pcrREG->PPROTSET3 = 0xFFFFFFFFU;

    /* bring SPI out of reset */
    spiREG2->GCR0 = 0U;
    spiREG2->GCR0 = 1U;
  • 0 in reply to Haggy
    TI__Guru 68920 points

    Haggy,

    Most likely,  you executed the above code from a CPU mode with privilege, such as SYSTEM mode.

    See the description of the Protection register below: