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RM48Lxx operation questions for HAZOP process

Bob Bacon
Genius 10815 points


Hello
My customer has some general questions about the operation of cpu cores and memory as part of their HAZOP process.

The Tech Ref Manual is a great start but have some additional questions to confirm their understanding.
I have made a few comments and suggestions but would appreciate your confirmation.

Having a quick read of the TRM, (not all 1600 or so pages) Each processor provide a compare bus which the CPU Compare module uses to detect a difference between the two processor states. Different areas of memory can have different memory check performed. For the flash memory the user needs to write the contents with a pre-generated ECC code. For the RAM, ( although not specifically clear) the ECC codes are generated on the fly. Therefore errors in Ram will be detected and to some degree corrected.

 

Is it correct that each processor uses a different sector of RAM or do they use the same Ram ? the reason for the question is where there is a single area of memory used by both processors :-

1                     The master core writes to the Processor RAM. Both master and slave processors read the RAM.

2                     If memory in the Master processor Core gets corrupted and then writes to RAM with the ECC an incorrect but valid parameter is written to memory, and will not be detected.

3                     If both processors act on the same RAM contents, and the Ram is corrupt due to previous actions, both cores will behave in the same way because they are reading the same previously corrupted data. Error undetected although the error is very specific and therefore extremely remote.

 

Is this correct ? As I said it helps when determining where errors will be detected during the HAZOP process.

 

Is there a description of what the Processor compare bus conveys to the CPU Compare Module ?

Many Thanks

Bob

  • 0
    TI__Guru 68950 points
    Bob,

    There is only one SRAM and it is shared by both CPUs.

    Only one CPU actually reads and writes the SRAM. The other CPU shadows the actions of the first CPU with the time delay documented.

    The second CPU produces the same signals as the first CPU does when it is told to write to the RAM but these are connected not to the switch fabric but to the core compare module.

    So if the primary CPU writes invalid data to the RAM, the write may complete with correct ECC but the error will [within the bounds of diagnostic coverage %age claimed] be detected by the core compare module. This may put some uncertainty into the 'recovery' procedure for example writing code that handles the core compare error may need to be suspicious about values in RAM. But this isn't a case where it's undetected.

    There is a list somewhere of the signals that go to the core compare module but it's pretty exhaustive, basically almost every signal that is on the boundary of the CPU. I'd need to dig up what this list exactly is, but it's a lot more signals than just the bus that goes to RAM.

    -Anthony