DCAN controller RAM initialization

Jules Patru

Hi,

I opened a recent topic regarding DMA control packets initialization a few days ago (see e2e.ti.com/.../553509) .

Now I am going further in my project and I have similar question related to DCAN controller:
In my system, I have two softwares that run one after one other: a bootloader and an applicative.
My bootloader and my applicative are both using DCAN controllers thus, I would like to reset the DCAN RAM memory by the same way than I did for DMA controls packets (memset from basis DCAN RAM address for a length of 0x60000.

I paid attention to enter TEST mode (Init bit and Test bit to 1 in CTL register) and to enable direct access to RAM (RDA bit in TEST register).
But when I try to perform the memset full of 0 to the DCAN RAM address, I can see that any issue occurs (not able to say exactly what, probably a data abort; error pin is enabled).
Do I forgot something prior to access RAM?

Thanks for help

Jules

over 9 years ago

0 Anthony F. Seely over 9 years ago

TI__Guru 68950 points

Hi Jules,

It may be the size of the memset.

You mention 'memset from basis DCAN RAM address for a length of 0x60000'

But note:

0 Jules Patru over 9 years ago in reply to Anthony F. Seely

Intellectual 380 points

Hi Anthony,

Thanks for your answer.
I did not see this table. I only used the SPNU514b (chapter 2.2.4.2).

If I understand well, I should perform three separate "memset". The first one shall use DCAN1 RAM base address and shall be 0x800 bytes long. The second and the third memset shall use DCAN2 and DCAN3 controllers RAM base address and shall be 0x800 long each.
Finally I should avoid accessing addresses that are greater or equal than DACNx controller RAM base address + 0x800.
Am I right?

Jules

0 Anthony F. Seely over 9 years ago in reply to Jules Patru

TI__Guru 68950 points

yes

Arm-based microcontrollers

Arm-based microcontrollers forum

DCAN controller RAM initialization