SSIDataPut confusion on TM4C123GH6PM

Other Parts Discussed in Thread: TM4C123GH6PM

I am using the following simple code to test master slave mode on SSI0 and SSI1 on TM4C123GH6PM. When I debug, I see that the SSIDataPut function does not modify the SSI_DR register for the SSI0 module, until the 8th call where it sets it to 1111111111111111. I don't understand why this is happening. I'm new to TIVA and I got this code from sample code snippets on the web, the workbook and the TIVAWARE documentation. Thank you in advance for the technical support.

#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_memmap.h"
#include "inc/hw_ssi.h"
#include "inc/hw_types.h"
#include "driverlib/ssi.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "driverlib/sysctl.h"

int main(void) {

	//set the system clock from the main oscillator which drives the 400MHz PLL,
	//there is a default divide by 2 in the clock path
	//System clock is set to 40 MHz
	SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);

	//Enable the SSI0 module, connect to power and system clock
	SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);

	//Enable the GPIO A ports for SSI0
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
	//Enable the GPIO D ports for SSI1
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);

	//Configure GPIO pin A2 to be the SSI0 clock port
	//Write the requested pin muxing value
	GPIOPinConfigure(GPIO_PA2_SSI0CLK);
	GPIOPinConfigure(GPIO_PD0_SSI1CLK);

	//Configure the GPIO pin A3 to be the SSI0 FSS port (acts as slave select)
	//Write the requested pin muxing value
	GPIOPinConfigure(GPIO_PA3_SSI0FSS);
	GPIOPinConfigure(GPIO_PD1_SSI1FSS);

	//Configure the GPIO pin A5 to be the SSI0 TX pin
	//Write the requested pin muxing value
	GPIOPinConfigure(GPIO_PA5_SSI0TX);
	GPIOPinConfigure(GPIO_PD2_SSI1RX);

	//configure the GPIO port A as SSI ports
	//first checks if base port is valid for SSI
	//then sets them to be peripheral driven
	//sets the push pull properties
	GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5|GPIO_PIN_3|GPIO_PIN_2);
	GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0);

	//Configures the synchronous serial interface.
	//SSI module base address, system clock driving SSI module, protocol, master or slave mode, bit rate, frame width(4-16)
	//Protocol in this case is Motorala frame with polarity 0 and phase 0,
	//this is an SPI configuration, refer to software documentation and datasheet
	//Rules to set bit rate:
	//FSSI >= 2 ∗ bit rate (master mode)
	//FSSI >= 12 ∗ bit rate (slave modes)
	SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, SSI_MODE_MASTER, 8000, 16);
	SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, SSI_MODE_SLAVE, 8000, 16);

	//Start the SSI interface
	SSIEnable(SSI1_BASE);
	SSIEnable(SSI0_BASE);

	//enable interrupts
	SSIIntEnable(SSI0_BASE, SSI_RXFF | SSI_RXTO | SSI_RXOR );
	SSIIntEnable(SSI1_BASE, SSI_RXFF | SSI_RXTO | SSI_RXOR );

	unsigned long number = 40000000;
	uint32_t data_var;

	while(1){
		//places data on transmit FIFO, if FIFO is full, waits until empty space available before returning
		SSIDataPut(SSI0_BASE, number);
		while(SSIBusy(SSI0_BASE))
		{
		}
		//provides a delay by executing a 3-instruction cycle repeatedly
		//input is the number of delay loops to perform
		//not a real time delay
		//SysCtlDelay(2000000);
		//waits until data is received before returning!
		//SSIDataGet(SSI1_BASE, &data_var);
		SSIDataGetNonBlocking(SSI1_BASE, &data_var);
		//SysCtlDelay(2000000);
		number++;
	}

}