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TMS570LC4357 flash read margin

Mathieu Patte
Intellectual 440 points

Hello,

Section 7.8.5 of the TRM describes the read margin diagostics that can be run on the flash memory. 

However I didn't find any description on how to run tests with either read margin mode enable. I saw that the flash programming API offers functions to do that, but is there another way to configure the flash in one of the read margin mode? (register configuration or CCS action?)

Mathieu

  • 0
    TI__Guru**** 191826 points
    Hi Mathieu,
    You can use the API Fapi_doMarginRead() to do the margin test but its usefulness is limited if there is only one bit that is margin in your read. The reason is that the margin test is only useful if the ECC can be disabled. With the ECC disabled, if a bit cell is marginal then you can read an incorrect value in read-margin mode. However, unlike other Hercules devices, the LC4357 has the ECC always active. This means that if a bit cell is marginal which should have been read incorrectly in margin mode will be corrected by the ECC. So in this case, you don't really know if any bit is marginal or not. However, if two or more bits are marginal during read-margin test then you can still see uncorrectable error.
  • 0 in reply to Charles Tsai
    Intellectual 440 points
    Hello,

    My idea was to configure the read mode and then dump the flash memory contents using the Code Composer Studio through the AHB-AP and therefore identifying the weak bits. Do you think this is feasible?

    Mathieu
  • 0 in reply to Mathieu Patte
    TI__Guru**** 191826 points

    Hi Mathieu,

     I discussed with the L2FMC userguide owner about the reason that why the read margin register is left out in the TRM. It looks like there is no strong reason to leave it out and perhaps it is a mistake that we will correct in the release of the TRM. Here is the register. Please note that whether you use CPU or AHB-AP or DMA to read the flash in margin mode the single bit error will be corrected. For DMA and other masters reading the L2 memories (L2 Flash or L2 SRAM) the ECC checking is done inside the CPU Interconnect Subsystem. However, if there is an ECC error the error address will be captured in the EPC module. Please refer to the EPC module for details.

     The below excerpt is from the internal design spec.

  • 0 in reply to Charles Tsai
    Intellectual 440 points
    Thanks Charles, that's the information I was looking for.

    Mathieu