HI Team,
Can you please review and answer the following from our mutual customer.
Very Respectfully,
Omid D.
(1) It will be necessary for us to update the program flash in the field. So far, we have not succeeded in erasing or programming the
F021 flash by code running on the the Hercules part (TMS570LS0432).
We are attempting to link in the TI-supplied HERCULESF021FLASHAPI package from your web site (www.ti.com/tool/f021/flashapi). We are aware that it must run from SRAM.
We would like to verify that we are using that package correctly. We have tried to link it with code generated by both the Keil compiler and gcc, the latter downloaded prebuilt from https://launchpad.net/gcc-arm-embedded (20160926 version). It appears that all systems work with standard elf files, but I have found confusing and sometimes conflicting descriptions of BE32 versus BE8, and where/how the distinction matters to the tool chain. Could you let us know exactly how the F021 code was built (compiler, options, etc)? I'd like to be sure we're using that code as intended. Any other hints or advice with respect to F021 programming would also be appreciated.
(2) We would like to understand the rules for when the side effects of writes to memory-mapped i/o registers can be guaranteed. For example, what is necessary to assure that interrupts from a functional block are masked after a write to such a register that includes the relevant mask bits? Because such blocks are outside of the ARM-defined architecture, I don't think that the CPU's barrier instructions are adequate. When working with ARM SOCs from other vendors, there have been rules such as "do a read after write unless otherwise specified for the particular register (e.g., poll for change)." I have not yet found a similar rule in the Hercules documentation. What's required?
