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Procedure to perform RAM and FLASH self tests ECC on RM57 board

Other Parts Discussed in Thread: RM57L843, HALCOGEN

Hi

I would like to perform the RAM and flash tests on RM57 for bare metal, with ECC. My current project has ESM disabled.

I have gone through the safety library version for RM57, it has different procedure to test sigle bit and multi bit ECC errors, with the help of EPC and ESM.

But the way the ESM and EPC are enabled and used in safety library is not clear to me.

Could somebody help me on

1. What is the test procedure to be followed to validate RAM and ROM

2. Is it EPC and ESM are mandatory to enable, to validate these components

3. Steps to enable the EPC and ESM

3. Does the tests need to run on only on boot mode, not in user mode

I am new to TI processor, and also low level coding. Please help on this.

 

Regards,

Kanth.

  • You have asked simple questions which require long answers. I will try to give you an overview and then you might want to follow up with more specific questions.

    On the RM57L843 device ECC is always enabled for the Flash and the main RAM. Single bit errors can be corrected and operation can continue. Multi bit errors are uncorrectable and usually imply that the MCU operation cannot continue. Uncorrectable errors generate an event out of the Cortex R5 CPU. That event goes to the ESM (Error Signaling Module) which generates an NMI (non-maskable interrupt) and a toggle of the nERROR pin.

    Single bit errors in the flash or RAM can be corrected and proper operation continues. To avoid the overhead of repeatedly correcting a hard single bit error the EPC (Error Profiling Controller) captures the address and the correct data in a content addressable memory (CAM). You can choose to generate an interrupt from the ESM when a single bit error is detected and corrected, or only when the CAM is full.

    1. What is the test procedure to be followed to validate RAM and ROM

    The safety manual, SPNU575, has many suggestions on testing the RAM and Flash contents, as well as checking the ECC logic which checks the contents on all reads and most writes. PBIST can be used as an initial flash test and CRC checks can be run periodically on critical Flash or RAM contents.

    2. Is it EPC and ESM are mandatory to enable, to validate these components

    As described above, the EPC and ESM are an integral part of the notification of errors in the flash or RAM.

    3. Steps to enable the EPC and ESM

    In the safety library file "HL_sys_startup.c" line calls esmInit() and line 477 calls epcInit(). esmInit() is defined in the file HL_esm.c. epcInit() is defined in the file HL_epc.c. All three files are generated by HALCoGen.

    3. Does the tests need to run on only on boot mode, not in user mode

    Some of the tests are run only at startup, others may be run periodically. Table 4 in appendix A of the safety Manual, SPNU575, identifies diagnostic features as continuous or periodic on demand.

  • Hi

    Thanks for your reply, This gives some clue on how to proceed,

    Currently I have taken the approach, to enable the ESM and EPC in HAL startup code, and called try to trigger the flash ECC fault like,

    retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_1BIT, TRUE, &failInfoFlash);

    Same as given in safety library,

     

     /*SAFETYMCUSW 58 S MR:14.3 <APPROVED> Comment_16*/        

    flashread = *(volatile uint32 *)flashBadECC1;

    if (((((sl_epcREG1->EPCERRSTAT & EPC_ERR_CAM_FULL) == EPC_ERR_CAM_FULL) ||                 ((sl_epcREG1->EPCERRSTAT & EPC_ERR_CAM_OVRFLW) == EPC_ERR_CAM_OVRFLW) ||                 (sl_epcREG1->CAMAVAILSTAT != regBkupCamAvail))) &&  ((((sl_esmREG->SR1[0]) & BIT(ESM_G1ERR_EPC_SERR))) == (BIT(ESM_G1ERR_EPC_SERR))))

    {                    

    /* Clear ESM status registers */                    

    sl_esmREG->SR1[0] = BIT(ESM_G1ERR_EPC_SERR);

    if(sl_epcREG1->CAMAVAILSTAT != regBkupCamAvail)

    {                

    /* Clear the CAM entries */                

    /* Set CAM indices to available */                

    for(content = 0U; content<32U; content++)

    {                    

    if((volatile uint32 *)(sl_epcREG1->CAM_CONTENT[content] & EPC_CAM_CONTENT_ADDR) == (volatile uint32 *)(flashBadECC1 & EPC_CAM_CONTENT_ADDR))

    {                        

    break;                    

    }                

    }                

    /* Calculate the index location */                

    index = content/4;                

    index = content - index*4;                

    content = content/4;                

    BF_SET(sl_epcREG1->CAM_INDEX[content], (uint32)(0x5u), EPC_CAM_INDEX_START(index), EPC_CAM_INDEX_LENGTH);            

    }

     *flash_stResult = ST_PASS;

    }

    else {                 

    *flash_stResult = ST_FAIL;        

    }

     

    But I am facing few problems like,

    1. Should this code need to be run in supervisory mode, is it calling calling these functions from boot main is not sufficient?

        how to switch to the supervisory mode, as I need to get the status of these tests from user mode.

     

    2. Does ESM or EPC will struck up any where.

     

    Regards,

    Kanth