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TMS570 devices - its Master peripherals

Jiri Janacek
Genius 3315 points
Other Parts Discussed in Thread: TMS570LS3137

Dear all,

please may you explain some wording used within Hercules documentation?

For EMIF module, there are three internal interfaces defined within TRM document

  • CPU
  • DMA
  • Master peripherals

What is meant by Master peripherals? I can understand that the built-in debug module (externally accessible e.g. via JTAG) can be identified as the Master peripheral in this scope. But please may we limit only on the normal operating/running mode of the device (the entire System-on-the-Chip)?

E.g. the Safety manual states "Bus masters to the level two device hierarchy include CPUs, bus master peripherals, debug bus masters, and general purpose direct memory access (DMA) controllers." in the chapter "Product Overview". What is behind? I think the "bus master peripherals" term here is more general than the above mentioned (related to the EMIF module).

Thanks for your clarification in advance,

Best regards

Jiri

  • 0
    Prodigy 105 points
    Jiri,
    The Architectural Block Diagram of each TRM depicts how the EMIF is connected to the rest of the device, as well as master peripherals.
    In some cases Hercules devices have peripherals that are bus masters such as HTU, FTU, DMM, and EMAC.
    Like the safety manual states all of these master peripherals will connect through a common interface such as VBUSM or the peripheral interconnect subsystem. These master peripherals could be configured to interact with any available address space within their abilities which may include the EMIF.

    Dave
  • 0
    TI__Expert 6985 points

    Jiri,

    Please note, that the master peripherals are listed in the device datasheet along with their access rights.

    Here is an example for the TMS570LS3137:

    Best Regards,
    Christian